Displaying 2 results from an estimated 2 matches for "trystor".
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trystore
2014 May 29
4
[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions
...ge_strong(...))":
%loaded = cmpxchg i32* %addr, i32 %oldval, i32 %newval seq_cst seq_cst
%success = icmp eq i32 %loaded, %oldval
br i1 %success, label %true, label %false
the control-flow here should be something like:
loop:
%loaded = load linked i32* %addr seq_cst
%trystore = icmp eq %loaded, %oldval
br i1 %trystore, label %store.cond, label %false
store.cond:
%success = store conditional i32 %newval, i32* %addr seq_cst
br i1 %success, label %true, label %loop
>From "return __c11_compare_exchange_strong(...);":
%loaded = cmpxch...
2017 May 30
3
[atomics][AArch64] Possible bug in cmpxchg lowering
...0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release
acquire*_
%v1 = extractvalue { i32, i1 } %v0, 1
ret i1 %v1
}
to the equivalent of the following on AArch64:
_*ldxr w8, [x0]*_
cmp w8, w1
b.ne .LBB0_3
// BB#1: // %cmpxchg.trystore
stlxr w8, w2, [x0]
cbz w8, .LBB0_4
// BB#2: // %cmpxchg.failure
mov w0, wzr
ret
.LBB0_3: // %cmpxchg.nostore
clrex
mov w0, wzr
ret
.LBB0_4:
orr w0, wzr, #0x1
ret
GCC instead...