Displaying 10 results from an estimated 10 matches for "trycandidate".
2017 Nov 23
3
mischeduler (pre-RA) experiments
Hi,
I have been experimenting for a while with tryCandidate() method of the
pre-RA mischeduler. I have by chance found some parameters that give
quite good results on benchmarks on SystemZ (on average 1% improvement,
some improvements of several percent and very little regressions).
Basically, I add a "latency heuristic boost" just above proce...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
> On Oct 13, 2017, at 1:46 PM, Matthias Braun <matze at braunis.de> wrote:
>
> Yes, I've run into the problem myself that the Pending queue isn't even checked with the tryCandidate() logic and so takes priority over all other scheduling decisions.
>
> I personally would be open to changes in this area. To start the brainstorming I could imagine that we move nodes below a target specific limit into the available queue instead of just when they hit their latency cycle li...
2017 Nov 25
2
mischeduler (pre-RA) experiments
>
> Of course, you want to duplicate as little of the generic scheduling logic
> as you can. So I think the challenge is how to expose the
> generic scheduler's functionality as a base class or composition of
> utilities so that defining your strategy doesn't require too much
> copy-paste.
Isn't GCNMaxOccupancySchedStrategy [1] already an example on
using
2019 Sep 10
2
MachineScheduler not scheduling for latency
...or "shouldReduceLatency should not be relevant at
MicroOpBufferSize = 1": are you suggesting that shouldReduceLatency
should effectively be changed to always return true on in-order CPUs?
Even with that change, latency comes pretty far down the list of
criteria tested in GenericScheduler::tryCandidate.
Thanks,
Jay.
On Mon, 9 Sep 2019 at 19:36, Andrew Trick <atrick at apple.com> wrote:
>
>
> > On Sep 9, 2019, at 4:22 AM, Jay Foad <jay.foad at gmail.com> wrote:
> >
> > Hi,
> >
> > I'm trying to understand why MachineScheduler does a poor job in...
2016 Oct 21
3
Prioritizing an SDNode for scheduling
...can do this by changing instruction scheduling heuristics. I think the
> more important question is if this correct always for all platforms.
>
> I don't know which scheduler you use. We use GenericScheduler and
> PostGenericScheduler before and after RA. These classes have a
> ::tryCandidate method which compares two instructions that can be legally
> scheduled and decide which of the two should be scheduled. Currently these
> method are target independent.
>
> The correctness question still remains open for me.
>
>
> On Thu, Oct 20, 2016 at 8:08 PM, Alex Susu via...
2016 Oct 28
2
mischeduler
...on't check for
// acyclic latency during PostRA, and highly out-of-order processors will
// skip PostRA scheduling.
if (!OtherResLimited) {
if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() >
Rem.CriticalPath)) {
Policy.ReduceLatency |= true;
Why !OtherResLimited? tryCandidate() has already checked for resource
balancing just
before this. To not do the latency check then only means falling back to
original
order.
/Jonas
2016 Oct 21
2
Prioritizing an SDNode for scheduling
Hello.
Is there a way to specify in the back end an (ISD::INLINEASM) SDNode to be scheduled
first under all circumstances? I need to specify something like node priority to schedule
the node before all other nodes in the SelectionDAG of the basic block.
(Using chain or glue edges in order to make a node first is not a good idea, since I
am doing this at instruction selection time, on
2019 Sep 09
2
Fwd: MachineScheduler not scheduling for latency
...ncy heuristic? Moving instructions around
can't really change whether the function is issue limited or not, but
it can definitely improve latency problems.
3. Why do we completely turn off the latency heuristic, rather than
just letting it take its usual (very low) priority in
GenericScheduler::tryCandidate?
4. Stepping back a bit, is MachineScheduler really trying to consider
latency at all in pre-ra mode? I see a comment that it "Schedules
aggressively for latency in PostRA mode", but what about pre-ra?
Of course we can and do override some of the generic logic in our
target, in lib/Targe...
2018 Nov 06
4
top-down vs. bottom-up list scheduling
Hello List!
I am looking at top-down vs. bottom-up list scheduling for simple(r) in-order
cores. First, for some context, below is a fairly representative pseudo-code
example of the sort of DSP-like codes I am looking at:
uint64_t foo(int *pA, int *pB, unsigned N, unsigned C) {
uint64_t sum = 0;
while (N-- > 0) {
A1 = *pA++;
A2 = *pA++;
B1 = *pB++;
B2 =
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
Hi,
I've been looking at the Machine Scheduler on Power PC. I am looking only
at the pre-RA machine scheduler and I am running it in the default
bi-directional mode (so, both top down and bottom up queues are
considered). I've come across an example where the scheduler picks a poor
ordering for the instructions which results in very high register pressure
which results in spills.