Displaying 5 results from an estimated 5 matches for "truncstorei8".
2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In
2013 Apr 12
1
[LLVMdev] Problem with Store of i8 in a global address
...",
[],
IIStore>
{
let mayStore = 1;
}
def : Pat<(atomic_store_8 (IcyflexCONST32_GP tglobaladdr:$global),
(i32 GPR32:$ra)),
(STdb tglobaladdr:$global, (i32 GPR32:$ra))>;
def : Pat <(truncstorei8 (i32 GPR32:$ra),
(myCONST32_GP tglobaladdr:$global)),
(STdb tglobaladdr:$global, (i32 GPR32:$ra))>;
However, this IR code is working for Hexagon and not for my
architecture, being Target Node #190
@j = common global i8 0, align 1
define i32 @main() nounwind {
ent...
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,
2012 Apr 18
0
[LLVMdev] [cfe-dev] LLVM Backend for Z80
...> unsigned char i=10;
> unsigned char a = 20;
> a = a+i;
> }
>
> the llc fails to generate .S file.
> I have only added this instruction to Z80InstrInfo.td
>
> def STORE16_trunc: Z80Instr<(outs), (ins GPR16:$src, GPR16:$dst),
> "ld_b ($dst),$src",
> [(truncstorei8 GPR16:$src, GPR16:$dst)]>;
>
> This is also MY PSEUDO instruction on Z80.
> Next I will try to handle this is real instructions, but for now I cannot make futher due to that assertions.
> Attached is my whole code + test files.
>
> I have tried to debug but the breakpoints an...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...:0)=Rt
>> -// memb(Rs+#u6:0)=#S8
>> -let AddedComplexity = 10, isPredicable = 1 in
>> -def STrib_imm_V4 : STInst<(outs),
>> - (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
>> - "memb($src1+#$src2) = #$src3",
>> - [(truncstorei8 s8ImmPred:$src3, (add IntRegs:$src1,
>> - u6_0ImmPred:$src2))]>,
>> +let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in
>> +def LDrih_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),
>> + (ins PredRegs:$src1,...