Displaying 4 results from an estimated 4 matches for "truewhentru".
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truewhentrue
2010 Oct 04
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
..."and" with this truncate call, which leads to your troubles later on.
It would seem that the truncate is created by:
TargetLowering::SimplifySetCC
...
if (N0.getOpcode() == ISD::SETCC &&
isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^
(N1C->getAPIntValue() != 1);
if (TrueWhenTrue)
return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
// Invert the condition.
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
CC = ISD::getSetCCInverse(C...
2010 Oct 04
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
...to your troubles later on.
>
> It would seem that the truncate is created by:
>
> TargetLowering::SimplifySetCC
>
> ...
>
>
> if (N0.getOpcode() == ISD::SETCC &&
> isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
> bool TrueWhenTrue = (Cond == ISD::SETEQ) ^
> (N1C->getAPIntValue() != 1);
> if (TrueWhenTrue)
> return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
>
> // Invert the condition.
> ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
>...
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
> Bill Wendling wrote:
>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>
>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>
>>>> Our architecture has 1-bit boolean predicate registers.
>>>>
>>>> I've defined comparison
>>>>
>>>> def
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Bill Wendling wrote:
> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>
>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>
>>> Our architecture has 1-bit boolean predicate registers.
>>>
>>> I've defined comparison
>>>
>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set