search for: trueval

...of LLVMContext & Module life cycles, and this is my first real look at llvm's source. This patch at least makes my problem go away; @@ -2195,11 +2200,11 @@ bool GVN::processInstruction(Instruction *I) { BasicBlock *Parent = BI->getParent(); bool Changed = false; - Value *TrueVal = ConstantInt::getTrue(TrueSucc->getContext()); + Value *TrueVal = ConstantInt::getTrue(BranchCond->getContext()); BasicBlockEdge TrueE(Parent, TrueSucc); Changed |= propagateEquality(BranchCond, TrueVal, TrueE); - Value *FalseVal = ConstantInt::getFalse(FalseSucc->getCont...

...rrectly passed to the MBlazeTargetLowering::EmitCustomSelect. > SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op, > SelectionDAG &DAG) const { > SDValue LHS = Op.getOperand(0); > SDValue RHS = Op.getOperand(1); > SDValue TrueVal = Op.getOperand(2); > SDValue FalseVal = Op.getOperand(3); > DebugLoc dl = Op.getDebugLoc(); > unsigned Opc; > > SDValue CompareFlag; > if (LHS.getValueType() == MVT::i32) { > Opc = MBlazeISD::Select_CC; > CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT:...

...tarted to create a new backend for a new RISC architecture. Now I need some help to get forward with my project. I'm quite new to compiling techniques so I'm sorry for the stupid questions. Question 1: My idea is to lower the select SDNode as follows: %res1 = %falseVal %res2 = setc %trueVal, %condition Where setc is conditional mov. The question is how can I make sure that %res1 and %res2 are assigned to the same phsyical register? (I'm assuming you can only define virtual register once, is this correct assumption?) Question 2: What kind of information if any the front end...

...d > this is my first real look at llvm's source. > > This patch at least makes my problem go away; > > @@ -2195,11 +2200,11 @@ bool GVN::processInstruction(Instruction *I) { > BasicBlock *Parent = BI->getParent(); > bool Changed = false; > > - Value *TrueVal = ConstantInt::getTrue(TrueSucc->getContext()); > + Value *TrueVal = ConstantInt::getTrue(BranchCond->getContext()); > BasicBlockEdge TrueE(Parent, TrueSucc); > Changed |= propagateEquality(BranchCond, TrueVal, TrueE); > > - Value *FalseVal = ConstantInt::getF...

I am trying to add support for select_cc. In ARM it can be implemented with: mov $dst, $falseVal cmp $a, $b moveq $dst, $trueVal My current strategy is to expand select_cc in two ARM nodes: ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag edge. ARM::CMP would then expand to "cmp $a, $b". This instruction has no results. It only alters the CPSR (current program status register). ARM::SELECT w...

...refactoring in > InstSimplify at r275911 that isn't in the branch, so I don't think the patch > will apply as-is. For safety, you could apply the one-line fix without > pulling the refactoring into the branch with this diff: > > - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); > + unsigned BitWidth = > + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); > > > > > On Fri, Jul 22, 2016 at 7:45 AM, Hans Wennborg <hans at chromium.org> wrote: >> >> Sanjay: let me know if this is something that...

Hi Rafael, > I am trying to add support for select_cc. In ARM it can be implemented > with: > > mov $dst, $falseVal > cmp $a, $b > moveq $dst, $trueVal The more normal ARM code, as produced by assembly writers and compilers that I've seen, is cmp $a, $b moveq $dst, $trueVal movne $dst, $falseVal e.g. at the end of a function returning r0 orr r0, r0, #0x40 cmp r0, #0xfe moveq r0, #1 movne r0, #0 since only one m...

...gt; InstSimplify at r275911 that isn't in the branch, so I don't think the patch >> will apply as-is. For safety, you could apply the one-line fix without >> pulling the refactoring into the branch with this diff: >> >> - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); >> + unsigned BitWidth = >> + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); >> >> >> >> >> On Fri, Jul 22, 2016 at 7:45 AM, Hans Wennborg <hans at chromium.org> wrote: >>> >>> Sanjay: le...

...11 that isn't in the branch, so I don't think the > patch > >> will apply as-is. For safety, you could apply the one-line fix without > >> pulling the refactoring into the branch with this diff: > >> > >> - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); > >> + unsigned BitWidth = > >> + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); > >> > >> > >> > >> > >> On Fri, Jul 22, 2016 at 7:45 AM, Hans Wennborg <hans at chromium.org > <jav...

...module '<stdin>'. >>>> 2. Running pass 'Combine redundant instructions' on function '@strsave' >>>> >>>> --- >>>> >>>> Looking at the code, the issue is with this line: >>>> >>>> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X), m_APInt(C))) >>>> && >>>> *Y == ~*C) >>>> >>>> In this case Y is a 128-bit APInt, and so is the value that C is >>>> extracted from, but the m_APInt matcher has code that...

...ion knows the // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = BB; ++It; // thisMBB: // ... // TrueVal = ... // setcc r1, r2, r3 // bNE r1, r0, copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMa...

...ion knows the // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = BB; ++It; // thisMBB: // ... // TrueVal = ... // setcc r1, r2, r3 // bNE r1, r0, copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMa...

...plifycfg -instcombine -loop-rotate -loop-vectorize -instcombine 1. Running pass 'Function Pass Manager' on module '<stdin>'. 2. Running pass 'Combine redundant instructions' on function '@strsave' --- Looking at the code, the issue is with this line: if (TrueVal == X && match(FalseVal, m_And(m_Specific(X), m_APInt(C))) && *Y == ~*C) In this case Y is a 128-bit APInt, and so is the value that C is extracted from, but the m_APInt matcher has code that calls getSplatValue() if the matched expression has vector type. So C ends up as an...

...gt; 1. Running pass 'Function Pass Manager' on module '<stdin>'. >> 2. Running pass 'Combine redundant instructions' on function '@strsave' >> >> --- >> >> Looking at the code, the issue is with this line: >> >> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X), m_APInt(C))) && >> *Y == ~*C) >> >> In this case Y is a 128-bit APInt, and so is the value that C is >> extracted from, but the m_APInt matcher has code that calls getSplatValue() >> if the matched ex...

...nserter for the // select_cc operation. What we want to do is turn this into // a series of instructions that in the end become a compare // and a cmov_logical { MachineOperand Dst = MI->getOperand(0); MachineOperand TrueVal = MI->getOperand(1); MachineOperand FalseVal = MI->getOperand(2); MachineOperand CCFlag = MI->getOperand(3); CC = (INSTCC::CondCodes)MI->getOperand(3).getImm(); // Here I want to get the destination register of SET_CC instruction and pl...

After discussions last night, I'm leaning towards going legit with all my pseudo expansions in Mips 16. Some I think I can clearly do by just putting in the proper side effects of implicit registers (T8 the condition code register as used by mips 16). But I'm still left with some pseudos that have jmp .+4 type instructions in them. The original Mips port was to Mips I and Mips I,

Hi, Given a function like x < 0 ? 0 : x We can lower it to bic x, x, asr 31 because we can test if CC==LT && RHS==TrueVal==0 && LHS==FalseVal Further, give a function x > 255 ? 255 : (x < 0 ? 0 :x), we should lower it to: usat x, #8 However, things become more complicated if we have ((x < 0 ? 0 :x) << n ) & mask ... Because it will first be converted to x < 0 ? 0 : ((x << n) &...

On Thu, Sep 11, 2008 at 6:14 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I am attempting to lower the selectCC instruction to the instruction set of > the backend I'm working on and I cannot seem to find a way to correctly > implement this instruction. I know how this instruction should get > implemented; I just have yet to find a way to do it. I want the select_cc

On Thu, Jan 15, 2015 at 1:26 PM, Nick Lewycky <nlewycky at google.com> wrote: > On 15 January 2015 at 13:10, Daniel Berlin <dberlin at dberlin.org> wrote: > >> Yes. >> I've attached an updated patch that does the following: >> >> 1. Fixes the partialalias of globals/arguments >> 2. Enables partialalias for cases where nothing has been unified to

...een, and a branch opcode to use. + + // To "insert" these instructions we actually have to insert their + // control-flow patterns. const BasicBlock *LLVM_BB = BB->getBasicBlock(); ilist<MachineBasicBlock>::iterator It = BB; ++It; - - // thisMBB: - // ... - // TrueVal = ... - // cmpTY ccX, r1, r2 - // bCC copy1MBB - // fallthrough --> copy0MBB - MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); - unsigned SelectPred = MI->getOperand(4)...