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...t;>> >>> And the DX and EX registers are defined this way: >> The regclasses look fine... So, you need to figure out why >> getRepRegClassFor() returns NULL in this case. > Well, that's rather easy :-) The register class is not registered in > the constructor of TriCoreTargetLowering. Maybe, some background is > missing here: > > - I added the ER register class for MVT::i64 and I had to take care of > quite a lot of stuff as the TriCore does not really support 64-bit > operations (it just offers these register pairs but almost no > operations working on t...

...sub_odd)]; >> } >> >> And the DX and EX registers are defined this way: > The regclasses look fine... So, you need to figure out why > getRepRegClassFor() returns NULL in this case. Well, that's rather easy :-) The register class is not registered in the constructor of TriCoreTargetLowering. Maybe, some background is missing here: - I added the ER register class for MVT::i64 and I had to take care of quite a lot of stuff as the TriCore does not really support 64-bit operations (it just offers these register pairs but almost no operations working on them). - Eli mentioned that i...

Fabian, > here are the definitions of these register classes: > > // Data register class > def DR : RegisterClass<"TriCore", [i32], 32, > (add D0, D1, D2, D3, D4, D5, D6, D7, > D8, D9, D10, D11, D12, D13, D14, D15)>; > > // Extended-size data register class > def ER :

...ceptional operations are division and multiplication, for instance. In the tablegen files these registers and the corresponding register class are modelled accordingly and the instruction selector also selects them. The paired 64bit register class is however not added within the constructor of the TriCoreTargetLowering class. So, at some point GetCostForDef is called for a MVT::i64 in connection with a division instruction and this call segfaults as there just is no matching register class available for TriCore. Unfortunately, just adding the register class for MVT::i64 does not help either. In that case th...

...he zext instruction from i32 to i64. In principle, this is very easy on the TriCore. Zext the argument in the lower part of the 64bit register pair and write 0 to higher part. Finally, these parts are glued together using ISD::BUILD_PAIR. However, when I try to insert such nodes into the DAG within TriCoreTargetLowering, I run into an assertion: llc: /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion `NumMIOperands >= II.getNumOperands() && NumMI...

...i32 to i64. In > principle, this is very easy on the TriCore. Zext the argument in the > lower part of the 64bit register pair and write 0 to higher part. > Finally, these parts are glued together using ISD::BUILD_PAIR. > However, when I try to insert such nodes into the DAG within > TriCoreTargetLowering, I run into an assertion: > > llc: > /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: > void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, > llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion > `NumMIOperands >= II.get...

...gt; principle, this is very easy on the TriCore. Zext the argument in the >> lower part of the 64bit register pair and write 0 to higher part. >> Finally, these parts are glued together using ISD::BUILD_PAIR. >> However, when I try to insert such nodes into the DAG within >> TriCoreTargetLowering, I run into an assertion: >> >> llc: >> /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: >> void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, >> llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion >> `Num...

...EX registers are defined this way: >>> >>> The regclasses look fine... So, you need to figure out why >>> getRepRegClassFor() returns NULL in this case. >> >> Well, that's rather easy :-) The register class is not registered in >> the constructor of TriCoreTargetLowering. Maybe, some background is >> missing here: >> >> - I added the ER register class for MVT::i64 and I had to take care of >> quite a lot of stuff as the TriCore does not really support 64-bit >> operations (it just offers these register pairs but almost no >>...

...DX and EX registers are defined this way: >>>> The regclasses look fine... So, you need to figure out why >>>> getRepRegClassFor() returns NULL in this case. >>> Well, that's rather easy :-) The register class is not registered in >>> the constructor of TriCoreTargetLowering. Maybe, some background is >>> missing here: >>> >>> - I added the ER register class for MVT::i64 and I had to take care of >>> quite a lot of stuff as the TriCore does not really support 64-bit >>> operations (it just offers these register pairs bu...

...ion and > multiplication, for instance. In the tablegen files these registers > and the corresponding register class are modelled accordingly and the > instruction selector also selects them. > > The paired 64bit register class is however not added within the > constructor of the TriCoreTargetLowering class. So, at some point > GetCostForDef is called for a MVT::i64 in connection with a division > instruction and this call segfaults as there just is no matching > register class available for TriCore. > > Unfortunately, just adding the register class for MVT::i64 does not &gt...

...is very easy on the TriCore. Zext the argument in the > >> lower part of the 64bit register pair and write 0 to higher part. > >> Finally, these parts are glued together using ISD::BUILD_PAIR. > >> However, when I try to insert such nodes into the DAG within > >> TriCoreTargetLowering, I run into an assertion: > >> > >> llc: > >> /home/scheler/git/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:704: > >> void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, > >> llvm::DenseMap<llvm::SDValue, unsigned int>&)...