Displaying 6 results from an estimated 6 matches for "tricoreregwithsubregs".
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
> This isn't really my area of expertise, but I think you're messing up
> your RegisterClass definition. Look at how ARM defines DTriple.
DTriple is untyped :) , because we do not have any valut type which
defines 3xi64.
However, the paired register needs to have type.
Fabian, what are the definitions of ER and DR register classes?
--
With best regards, Anton Korobeynikov
Faculty
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...2, E4, E6, E8, E10, E12, E14)> {
let SubRegClasses = [(DR sub_even, sub_odd)];
}
And the DX and EX registers are defined this way:
def D0 : TriCoreReg<0, "d0">, DwarfRegNum<[0]>;
...
def D15 : TriCoreReg<15, "d15">, DwarfRegNum<[15]>;
def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]>, DwarfRegNum<[32]>;
def E2 : TriCoreRegWithSubregs<2, "e2", [D2, D3]>, DwarfRegNum<[33]>;
...
def E14 : TriCoreRegWithSubregs<14, "e14", [D14, D15]>, DwarfRegNum<[39]>;
Ciao, Fabian
2012 Aug 21
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...t's implementation of
> SelectionDAGISel::Select.
OK, I rechecked my problem and I hope I can now describe it more precisely:
1. The TriCore supports register pairs forming 64.bit registers. These
64-bit registers are defined like this and form the "ER" register
class:
def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]>, DwarfRegNum<[32]>;
...
def E14 : TriCoreRegWithSubregs<14, "e14", [D14, D15]>, DwarfRegNum<[39]>;
2. The TriCore has some instructions that make use of an arbitrary
register pair, for example integer division (consisting of a sing...
2012 Aug 21
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
...ionDAGISel::Select.
>
> OK, I rechecked my problem and I hope I can now describe it more precisely:
>
> 1. The TriCore supports register pairs forming 64.bit registers. These
> 64-bit registers are defined like this and form the "ER" register
> class:
>
> def E0 : TriCoreRegWithSubregs<0, "e0", [D0, D1]>, DwarfRegNum<[32]>;
> ...
> def E14 : TriCoreRegWithSubregs<14, "e14", [D14, D15]>, DwarfRegNum<[39]>;
>
> 2. The TriCore has some instructions that make use of an arbitrary
> register pair, for example integer divisi...
2012 Aug 20
0
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler
<fabian.scheler at gmail.com> wrote:
> Hi Eli,
>
>>>>> 2. Storing arbitrary sized integers
>>>>>
>>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for
>>>>> loading/storing e.g. i33 integers from/into global variable. The
>>>>> questions
2012 Aug 20
2
[LLVMdev] Passing return values on the stack & storing arbitrary sized integers
Hi Eli,
>>>> 2. Storing arbitrary sized integers
>>>>
>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for
>>>> loading/storing e.g. i33 integers from/into global variable. The
>>>> questions are the same as regarding feature 1: How important is this
>>>> feature? Is it save to ignore it? Is there