search for: tricoreinstrinfo

...n lowering a specific instruction within the TargetLowering? > > If you do dump(CurDAG) then it will resolve machine nodes for you. > See llvm/include /llvm/CodeGen/SelectionDAGNodes.h > By using dump(CurDAG) I was finally able to find out the problematic instruction. It was defined in TriCoreInstrInfo.td but did not have an associated pattern (the pattern is empty '[]'). Furthermore, this instruction was not used anywhere else in the TriCore back-end, so I commented it out. This resulted in the same assertion being triggered and again no pattern was associated with the problematic instru...

...ithin the TargetLowering? > > > > If you do dump(CurDAG) then it will resolve machine nodes for you. > > See llvm/include /llvm/CodeGen/SelectionDAGNodes.h > > > > By using dump(CurDAG) I was finally able to find out the problematic > instruction. It was defined in TriCoreInstrInfo.td but did not have an > associated pattern (the pattern is empty '[]'). Furthermore, this > instruction was not used anywhere else in the TriCore back-end, so I > commented it out. This resulted in the same assertion being triggered > and again no pattern was associated with th...

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Fabian Scheler > Sent: Wednesday, August 15, 2012 9:12 AM > To: LLVM Developers Mailing List > Subject: [LLVMdev] More Back-End Porting Troubles > > Hi LLVM-Folks, > > as mentioned in an earlier post >

Hi LLVM-Folks, as mentioned in an earlier post (http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051677.html) I am currently working on a Back-End for the TriCore processor. Currently, I am struggling as LLVM could not select zext and load, for instance, so some of the testcases in test/CodeGen/Generic are not successfully compiled by my back-end. Furthermore, I am completely puzzled by the