Displaying 4 results from an estimated 4 matches for "trcd".
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tcd
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote:
> I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
The COPY instruction handles subreg operations with less
2014 Aug 25
0
[PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.
...ctivate delay. </doc>
> + </bitfield>
> + <bitfield high="23" low="17" name="tRAS">
> + <doc> Activate to precharge delay. </doc>
> + </bitfield>
> + <bitfield high="31" low="24" name="tRCD">
> + <doc> RAS# to CAS# Delay. </doc>
> </bitfield>
> </reg32>
>
> <reg32 offset="0x294" name="MEM_TIMINGS_1" variants="NVC0-">
> + <bitfield high="3" low="0" name="tCL...
2014 Aug 25
12
[PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.
...<doc> Refresh to activate delay. </doc>
+ </bitfield>
+ <bitfield high="23" low="17" name="tRAS">
+ <doc> Activate to precharge delay. </doc>
+ </bitfield>
+ <bitfield high="31" low="24" name="tRCD">
+ <doc> RAS# to CAS# Delay. </doc>
</bitfield>
</reg32>
<reg32 offset="0x294" name="MEM_TIMINGS_1" variants="NVC0-">
+ <bitfield high="3" low="0" name="tCL">
+ <doc> Row Cyc...