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...i8 predicate register that represents the true predicate as -1 with a sign extend like this: addRegisterClass(MVT::i8, &Hexagon::PredRegsRegClass); setBooleanContents(ZeroOrNegativeOneBooleanContent); and I'm calling this code just before computeRegisterProperties, that builds the TransformToType table specifying the type promotions: i1 -> i8 i8 -> i8 (legal) i16 -> i32 i32 -> i32 (legal) This would be fine if the register for i8 could be used for any integer operation (as in x86 for instance), but on Hexagon, predicate registers can only be used in a few logical operations....

...presents the true predicate as -1 with a sign extend like this: > > addRegisterClass(MVT::i8,&Hexagon::PredRegsRegClass); > setBooleanContents(ZeroOrNegativeOneBooleanContent); > > and I'm calling this code just before computeRegisterProperties, that > builds the TransformToType table specifying the type promotions: > > i1 -> i8 > i8 -> i8 (legal) > i16 -> i32 > i32 -> i32 (legal) > > This would be fine if the register for i8 could be used for any > integer operation (as in x86 for instance), but on Hexagon, predicate > register...

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > however, is that they are 8 bits.  The reason for this is

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

.../llvm/Target/TargetLowering.h | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) commit 1c1a80ce4db07988a839af7aa7a58acd6164364f Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Wed Dec 5 12:55:45 2012 +0100 Change TargetLowering::TransformToType to contain MVTs, instead of EVTs. include/llvm/Target/TargetLowering.h | 18 +++++++++--------- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) commit c53e2efbd52ac2a4690fe69c8ea4acad113956e0 Author: Patrik Hägglund <patrik...