Displaying 3 results from an estimated 3 matches for "transformsfrom".
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
>
> Currently, we rely on switch tables to transform between formats. However,
> we would like to have a different mechanism to represent these relationships
> instead of switch tables. I am thinking of modeling these relations in
> HexagonInstrInfo.td file and use TableGen to generate a table with
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
...(Predicate true)
Add register immediate - R1 = add(R2, #12) --
\
\---- if (!p0) R1 = add(R2,
#12)
(predicate false)
multiclass Add_rr < IFormat TransformsFrom> {
def #NAME# : V2_A2_add, RelationMap < TransformsFrom, Format_rr>;
defm _pt : V2_A2_padd, RelationMap < Format_rr, Format_predt, ["rr"]>;
defm _pf : V2_A2_padd, RelationMap < Format_rr, Format_predf, ["rr"] >; }
multiclass Add_ri < IFormat Transf...
2012 Aug 01
3
[LLVMdev] TableGen related question for the Hexagon backend
Hi,
I'm looking for some suggestions on a problem related to the Hexagon
backend.
Hexagon architecture allows instructions in various formats. For example, we
have 3 variations of the add instruction as defined below:
ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 =
add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is
true ADDrr_np :