search for: tracksregliveness

Displaying 7 results from an estimated 7 matches for "tracksregliveness".

2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
I've looked into that and it's not going to be simple, unfortunately. Here's the original example again: --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed %r0 J2_jump %bb.3, implicit-def %pc bb.2...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
The comment in test/CodeGen/X86/branchfolding-undef.mir states that such merging is legal, however doing so can actually generate wrong code: Consider this (valid code): --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed %r0 J2_jump %bb.3, implicit-def %pc bb.2...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
...<llvm-dev at lists.llvm.org> wrote: >> >> The comment in test/CodeGen/X86/branchfolding-undef.mir states that such merging is legal, however doing so can actually generate wrong code: >> >> Consider this (valid code): >> >> --- >> name: fred >> tracksRegLiveness: true >> >> body: | >> bb.0: >> successors: %bb.1, %bb.2 >> J2_jumpt undef %p0, %bb.2, implicit-def %pc >> J2_jump %bb.1, implicit-def %pc >> >> bb.1: >> successors: %bb.3 >> %r0 = L2_loadruh_io undef %r0, 0 &...
2019 Sep 09
2
LiveInterval error with 2 dead defs
Hi, I’m hitting a machine verifier error in a trivial testcase which I don’t understand. There are 2 dead defs of the same register: --- name: multiple_connected_compnents_dead tracksRegLiveness: true body: | bb.0: dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ... The live intervals look OK to me with 1 valno per instruction, for the life of the instruction like I would expect. The verifier does not like it howev...
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
...gt; On Jul 28, 2017, at 11:08 AM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: >> >> I've looked into that and it's not going to be simple, unfortunately. >> >> Here's the original example again: >> >> --- >> name: fred >> tracksRegLiveness: true >> >> body: | >> bb.0: >> successors: %bb.1, %bb.2 >> J2_jumpt undef %p0, %bb.2, implicit-def %pc >> J2_jump %bb.1, implicit-def %pc >> >> bb.1: >> successors: %bb.3 >> %r0 = L2_loadruh_io undef %r0, 0 &...
2018 May 16
0
Bug in TailDuplicator?
...org/pipermail/llvm-dev/attachments/20180516/6696fd59/attachment.bin> -------------- next part -------------- # RUN: llc -mtriple=XXX -O0 -run-pass block-placement -o - %s | FileCheck %s --- | define void @main(i8* %x) { entry: ret void } ... --- name: main alignment: 5 tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 liveins: %r0, %r8 conditional_branch %r0, 2, %bb.2 unconditional_branch %bb.1 bb.1: successors: %bb.1, %bb.8 conditional_branch %r8, 0, %bb.8 unconditional_branch %bb.1 bb.2: successors: %bb.3,...
2019 Oct 07
2
LiveInterval error with 2 dead defs
...PM, Arsenault, Matthew <Matthew.Arsenault at amd.com<mailto:Matthew.Arsenault at amd.com>> wrote: Hi, I’m hitting a machine verifier error in a trivial testcase which I don’t understand. There are 2 dead defs of the same register: --- name: multiple_connected_compnents_dead tracksRegLiveness: true body: | bb.0: dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ... The live intervals look OK to me with 1 valno per instruction, for the life of the instruction like I would expect. The verifier does not like it howev...