search for: tpidr_el0

Hi Tim, Thank you for your response. I need that immediate value latter to concatenate to registers' names (which I am doing during assembly printing). Also just Updating some status for my questioin: I have continued with using *Defs* list. It allows me to keep Registers as an implicit operands of /*MachineInstr*/ and later during its lowering pass them to the /*MCInstr*/. Now seems I need

Hi, would like to use LLVM as backend for a compiler. One of the features I would like to implement is segment based addressing for position independent data. For some it may sound strange, for others the opposite. No need to write complex story. Imagine you have a custom alocator that manages an area of 1GB of memory. Your application uses a custom allocator to allocate memory inside this area,

...02 a9 stp x29, x30, [sp, #32] 2d4c8: fd 83 00 91 add x29, sp, #32 2d4cc: 08 01 00 d0 adrp x8, #139264 2d4d0: 08 49 47 f9 ldr x8, [x8, #3728] 2d4d4: 49 d0 3b d5 mrs x9, TPIDR_EL0 2d4d8: 28 69 68 f8 ldr x8, [x9, x8] 2d4dc: 08 7d 40 b2 orr x8, x8, #0xffffffff 2d4e0: 08 05 00 91 add x8, x8, #1 2d4e4: a2 13 00 d1 sub x2, x29, #4 2d4e8: e9 03 08 aa...

...9, x30, [sp, #32] >> 2d4c8: fd 83 00 91 add x29, sp, #32 >> 2d4cc: 08 01 00 d0 adrp x8, #139264 >> 2d4d0: 08 49 47 f9 ldr x8, [x8, #3728] >> 2d4d4: 49 d0 3b d5 mrs x9, TPIDR_EL0 >> 2d4d8: 28 69 68 f8 ldr x8, [x9, x8] >> 2d4dc: 08 7d 40 b2 orr x8, x8, #0xffffffff >> 2d4e0: 08 05 00 91 add x8, x8, #1 >> 2d4e4: a2 13 00 d1 sub x2, x29, #4 >&gt...

...2d4c8: fd 83 00 91 add x29, sp, #32 > >>> 2d4cc: 08 01 00 d0 adrp x8, #139264 > >>> 2d4d0: 08 49 47 f9 ldr x8, [x8, #3728] > >>> 2d4d4: 49 d0 3b d5 mrs x9, TPIDR_EL0 > >>> 2d4d8: 28 69 68 f8 ldr x8, [x9, x8] > >>> 2d4dc: 08 7d 40 b2 orr x8, x8, #0xffffffff > >>> 2d4e0: 08 05 00 91 add x8, x8, #1 > >>> 2d4e4: a2 13 00 d1...

...in most cases (on x86). On ARM there is > >> definitely a cost. > >> > > hm... why? You cannot have indexed addressing? > What I need is a way to force > The code that needs to be emitted is roughly: > [..."segment"-offset into x1...] > mrs x0, tpidr_el0 > ldr xD, [x0, x1] > > That's a more complex addressing mode and an additional MRS > instruction over the usual sequence. You also lose the ability to fold > the actual address-computation into the LDR. > but this is the price you pay always for RISC vs. x86, or? Probably...

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

Hi, When using Wine to run Windows ARM64 executables on Linux, there's one major ABI incompatibility between the two; Windows treats the x18 register as the reserved platform register, while it is free to be clobbered anywhere in code on Linux. The Wine code sets up this register before passing control over to the Windows executable code, but whenever the Windows code calls a function

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I