search for: tp58975p61607

Displaying 3 results from an estimated 3 matches for "tp58975p61607".

2013 Sep 28
1
[LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3
Hi Andy, Are there plans to change the default scheduler for ARM targets in 3.4? -Slava -- View this message in context: http://llvm.1065342.n5.nabble.com/MI-Scheduler-vs-SD-Scheduler-tp58975p61607.html Sent from the LLVM - Dev mailing list archive at Nabble.com.
2013 Sep 24
0
[LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3
On Sep 17, 2013, at 11:04 AM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > 1. The SD schedulers significantly impact the spill counts and the execution times for many benchmarks, but the machine instruction (MI) scheduler in 3.3 has very limited impact on both spill counts and execution times. Is this because most of you work on MI did not make it into the 3.3 release? We
2013 Sep 17
11
[LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3
Hi Andy, We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. Here are our main findings: 1. The SD schedulers significantly impact the spill counts and the execution times for many