search for: topq

...but only 1 load can be executed at a time. Pick Top CLUSTER Scheduling SU(43) %vreg46<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 48; mem:LD4[<unknown>] SGPR_32:%vreg46 SReg_128:%vreg9 SReg_32: 45 > 44(+ 0 livethru) VS_32: 51 > 18(+ 0 livethru) Ready @46c HWLGKM +1x105u TopQ.A BotLatency SU(43) 78c *** Max MOps 1 at cycle 46 Cycle: 47 TopQ.A TopQ.A @47c Retired: 47 Executed: 47c Critical: 47c, 47 MOps ExpectedLatency: 10c - Latency limited. BotQ.A RemLatency SU(1698) 99c TopQ.A + Remain MOps: 1692 TopQ.A RemLatency SU(201) 97c BotQ.A + Remain MOps: 1647...

Hi, I have a program with over 100 loads (each with a 10 cycle latency) at the beginning of the program, and I can't figure out how to get the machine scheduler to intermix ALU instructions with the loads to effectively hide the latency. It seems the issue is with load clustering. I restrict load clustering to 4 at a time, but when I look at the debug output, the loads are always being

...te: usr/src/cmd/lp/cmd/lpadmin/Makefile update: usr/src/cmd/lp/cmd/lpadmin/do_printer.c update: usr/src/cmd/lp/cmd/lpadmin/lpadmin.c update: usr/src/cmd/lp/cmd/lpadmin/lpadmin.h update: usr/src/cmd/lp/cmd/lpadmin/rmdest.c update: usr/src/cmd/lp/cmd/lpc/process.c update: usr/src/cmd/lp/cmd/lpc/topq.c update: usr/src/cmd/lp/cmd/lpsched/Makefile update: usr/src/cmd/lp/cmd/lpsched/disp1.c update: usr/src/cmd/lp/cmd/lpsched/dispatch.h update: usr/src/cmd/lp/cmd/lpsched/disptab.c update: usr/src/cmd/lp/cmd/lpsched/exec.c update: usr/src/cmd/lp/cmd/lpsched/validate.c update: usr/src/cmd/lp/c...