search for: tomson

...possible, and then generating rol by hand. Marking it as "expand" would likely stop the DAG combiner from creating it. Then you could "preprocess" the selection DAG before the instruction selection and do the pattern matching yourself. -Krzysztof On 11/3/2016 4:24 PM, Phil Tomson via llvm-dev wrote: > I could try setting ISD::ROTL to Expand... however, we do have a rol op > and we'd like the ISD::ROTL to map to it. If I set it to Expand it's > not going to do that, right? > > I think in this case we're just getting the ISD::ROTL a bit too soon in...

...chineScheduler all settings are the same regardless of the optimisation level, however the MachineScheduler is disabled as a whole in TargetPassConfig.cpp when optimized regalloc is not enabled (which I believe happens for everything except -O0). - Matthias > On Sep 12, 2016, at 10:41 AM, Phil Tomson via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > As a follow on question: which of these options are already enabled when compiling with -O3? > > Phil > > On Mon, Sep 12, 2016 at 10:37 AM, Phil Tomson <phil.a.tomson at gmail.com <mailto:phil.a.tomson at gmail.co...

...instructions (utils/schedcover.py). It is very simplistic and takes as input the debug output of tablegen. There are some usage comments at the beginning. Regards, Christof From: llvm-dev <llvm-dev-bounces at lists.llvm.org<mailto:llvm-dev-bounces at lists.llvm.org>> on behalf of Phil Tomson via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> Reply-To: Phil Tomson <phil.a.tomson at gmail.com<mailto:phil.a.tomson at gmail.com>> Date: Wednesday, 20 April 2016 23:06 To: LLVM Developers Mailing List <llvm-dev at lists.llvm.org<mailto:l...

Setting the ISD::ROTL to Expand doesn't work? (via SetOperation) You could also do a Custom hook if that's what you're looking for. On Thu, Nov 3, 2016 at 5:12 PM, Phil Tomson <phil.a.tomson at gmail.com> wrote: > ... or perhaps to rephrase: > > In 3.9 it seems to be doing a smaller combine much sooner, whereas in 3.6 > it deferred that till later in the instruction selection pattern matching - > the latter was giving us better results because it se...

On Wed, Dec 2, 2015 at 10:39 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk > wrote: > On 2 Dec 2015, at 18:30, Phil Tomson <phil.a.tomson at gmail.com> wrote: > > > >> If you want to pass LLVM arguments to clang, then you must prefix them > with -llvm (e.g. -mllvm -loops -mllvm lcssa). > > > > > > I just tried this: > > CFLAGS += -mllvm adce -mllvm loops -mllvm loop-simpl...

On Fri, Nov 6, 2015 at 11:10 AM, Tim Northover <t.p.northover at gmail.com> wrote: > On 6 November 2015 at 11:00, Phil Tomson <phil.a.tomson at gmail.com> wrote: > > With 3.6 I get an unused argument warning with -enable-pie: > > > > $ clang -v -emit-llvm -enable-pie -O0 -S global_dat.c -o > > global_dat_x86_pie.ll > > Yes, it's an llc option not a Clang option. It actually looks li...

...need different target hooks. > > > > Sergei > > > > --- > > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > > > > *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Phil > Tomson via llvm-dev > *Sent:* Wednesday, April 20, 2016 12:51 PM > *To:* LLVM Developers Mailing List <llvm-dev at lists.llvm.org> > *Subject:* [llvm-dev] How to get started with instruction scheduling? > Advice needed. > > > > I need to add instruction scheduling for a new t...

I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: -misched-topdown -misched-bottomup The description in MachineScheduler.cpp says: "Force top-down list scheduling" and "Force bottom-up list scheduling" Which isn't too helpful - where might I want to use these?

On Fri, Nov 6, 2015 at 10:46 AM, Tim Northover <t.p.northover at gmail.com> wrote: > On 6 November 2015 at 10:32, Phil Tomson via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > So if I were to pass this .ll file (global_dat_x86_pie.ll) to llc how > would > > llc know that the PIE Level is 2? Is this an oversight, bug, or expetcted > > behaviour with a different workaround? > > It lo...

On Wed, Dec 2, 2015 at 10:17 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk > wrote: > On 2 Dec 2015, at 17:56, Phil Tomson via llvm-dev <llvm-dev at lists.llvm.org> > wrote: > > > > Now my intent is to figure out which optimization pass is causing the > problem by trying each one until I hit the same problem as with -O1, but > clang itself doesn't seem to allow these commandline options,...

On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > We improved our instruction itineraries and now we're seeing our > testcases for fence instructions break. > > > > For example, we have this testcase: > > > > @write_me = external global...

...rce code can be found here: > PPCInstrInfo::getInstrLatency. You can also look at getStageLatency in > include/llvm/MC/MCInstrItineraries.h. From this two you can probably find > other relevant places. > > Hope this helps > Ehsan > > > On Mon, Jun 6, 2016 at 2:37 PM, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> In our architecture loads from certain memory locations take a long time >> to complete (on the order of 150 clock cycles). Since we don't have a way >> to tell at compile time if the address being loaded fro...

...aylor <ryta1203 at gmail.com> wrote: > I believe some of the ISDs were introduced to allow for DAG optimizations > under the assumption that some of the major architectures directly support > these types of instructions. > > -Ryan > > On Wed, Nov 2, 2016 at 6:24 PM, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed >> one of our code generation tests is breaking in 3.9. >> >> The test is: >> >> ; RUN: llc < %s -march=xstg | File...

On Thu, Jan 7, 2016 at 1:35 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org > wrote: > On 1/7/2016 3:25 PM, Phil Tomson wrote: > >> >> That's better, but now I get: >> >> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires >> exactly 2 operands! >> >> Which makes some sense as XSTGRELADDR is defined as: >> def SDT_RELADDR : SDTypeProfile...

Thanks, that worked. So that's basically a cast, then? I have another question about expanding that pseudo op, but I'll post it separately. Phil On Wed, Jan 13, 2016 at 10:26 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/13/2016 11:59 AM, Phil Tomson via llvm-dev wrote: > >> >> XSTGInstrInfo.td:908:73: error: expected variable name in dag literal >> >> i64:(XSTGMVINI i64:$addr) >> ^ >> How can this be resolved? >> > > Try...

On Mon, Jul 11, 2016 at 2:20 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 7/11/2016 3:27 PM, Phil Tomson via llvm-dev wrote: > >> >> I guess I'm a bit surprised that -O3 wouldn't automatically do what I've >> done in the second version of the C code when generating code from the >> first version? >> > > This is most likely because a, b, and c are assu...

On 1/7/2016 5:54 PM, Phil Tomson wrote: > I got it to compile by changing to: > def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, > SDTCisSameAs<0, 1>]>; > def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; > > let Uses= [GRP] in { > def RelAddr...

On 1/15/2016 2:57 PM, Phil Tomson wrote: > > > I see the following in my SelectCode (in XSTGGenDGISel.inc): > > > /*2235*/ OPC_SwitchOpcode /*2 cases */, 27, > TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266 > /*2239*/ OPC_RecordChild0, // #1 = $addr > /*2240*/ OPC_MoveChild, 0, &gt...

0 down vote favorite <http://stackoverflow.com/questions/34049511/how-to-pass-optimization-passes-to-clang#> I'm trying to debug an issue for a new target where a testcase fails with -O1 optimization and passes with -O0 optimization. I got a list of optimization passes being performed when 'clang -O1' is called like this: llvm-as < /dev/null | opt -O1 -disable-output

We improved our instruction itineraries and now we're seeing our testcases for fence instructions break. For example, we have this testcase: @write_me = external global i32 @read_me = external global i32 ; Function Attrs: nounwind define i32 @xstg_intrinsic(i32 %foo) #0 { entry: ; CHECK: store r0, r1, 0, 32 ; CHECK-NEXT: fence 2 %foo.addr = alloca i32, align 4 store i32 %foo,