search for: tmp_idx

...c_init_qp_minus26 : 6; // 32 0..5 > signed chroma_qp_index_offset : 5; // 32 6..10 > signed second_chroma_qp_index_offset : 5; // 32 11..15 > > unsigned weighted_bipred_idc : 2; // 34 0..1 > unsigned fifo_dec_index : 7; // 34 2..8 > unsigned tmp_idx : 5; // 34 9..13 -> CurrColIdx (index of associated co-located motion data buffer) > unsigned frame_number : 16; // 34 14..29 > unsigned u34_3030 : 1; // 34 30..30 pp.u34[30:30] > unsigned u34_3131 : 1; // 34 31..31 pad? > > uint32_t field_order_cnt...

On Thu, Nov 21, 2013 at 5:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Thu, Nov 21, 2013 at 5:07 PM, Benjamin Morris <bmorris at nvidia.com> wrote: >> On 11/19/2013 08:16 PM, Ilia Mirkin wrote: >>> Hello, >>> >>> I hope this is an appropriate style of request for this forum. I added >>> code to support video decoding on the tesla

...rmat_idc unsigned pic_order_cnt_type : 2; // 31 6..7 signed pic_init_qp_minus26 : 6; // 32 0..5 signed chroma_qp_index_offset : 5; // 32 6..10 signed second_chroma_qp_index_offset : 5; // 32 11..15 unsigned weighted_bipred_idc : 2; // 34 0..1 unsigned fifo_dec_index : 7; // 34 2..8 unsigned tmp_idx : 5; // 34 9..13 -> CurrColIdx (index of associated co-located motion data buffer) unsigned frame_number : 16; // 34 14..29 unsigned u34_3030 : 1; // 34 30..30 pp.u34[30:30] unsigned u34_3131 : 1; // 34 31..31 pad? uint32_t field_order_cnt[2]; // 38, 3c struct { // 40 // 0x00223102 //...

Create the ref_bo without any storage type flags set for now. The issue probably arises from our use of the additional buffer space at the end of the ref_bo. It should probably be split up in the future. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Tested-by: Martin Peres <martin.peres at labri.fr> Cc: "10.0" <mesa-stable at lists.freedesktop.org> ---

...nouveau/nouveau_vp3_video_vp.c +++ b/src/gallium/drivers/nouveau/nouveau_vp3_video_vp.c @@ -365,7 +365,7 @@ nouveau_vp3_fill_picparm_h264_vp(struct nouveau_vp3_decoder *dec, refs[j] = (struct nouveau_vp3_video_buffer *)d->ref[i]; h->refs[j].fifo_idx = j + 1; h->refs[j].tmp_idx = refs[j]->valid_ref; - assert(dec->refs[refs[j]->valid_ref].vidbuf == refs[j]); +// assert(dec->refs[refs[j]->valid_ref].vidbuf == refs[j]); h->refs[j].field_order_cnt[0] = d->field_order_cnt_list[i][0]; h->refs[j].field_order_cnt[1] = d->field_or...

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which