Displaying 20 results from an estimated 45 matches for "tmp8".
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2010 Jan 29
2
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
...* res) {
res->y = a.y;
}
int main(void) {
float3 a;
float3 res;
test(a, &res);
}
llvm-gcc -c -emit-llvm -O3 produces this:
%struct.float3 = type { float, float, float }
define void @test(double %a.0, float %a.1, %struct.float3* nocapture
%res) nounwind noinline {
entry:
%tmp8 = bitcast double %a.0 to i64 ; <i64> [#uses=1]
%tmp9 = zext i64 %tmp8 to i96 ; <i96> [#uses=1]
%tmp1 = lshr i96 %tmp9, 32 ; <i96> [#uses=1]
%tmp2 = trunc i96 %tmp1 to i32 ; <i32> [#uses=1]
%tmp3 = b...
2010 Jan 29
0
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
Hi Ralf,
> llvm-gcc -c -emit-llvm -O3 produces this:
>
> %struct.float3 = type { float, float, float }
> define void @test(double %a.0, float %a.1, %struct.float3* nocapture
> %res) nounwind noinline {
> entry:
> %tmp8 = bitcast double %a.0 to i64 ; <i64> [#uses=1]
> %tmp9 = zext i64 %tmp8 to i96 ; <i96> [#uses=1]
> %tmp1 = lshr i96 %tmp9, 32 ; <i96> [#uses=1]
> %tmp2 = trunc i96 %tmp1 to i32 ; <i32> [#uses...
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
...=2]
%tmp4 = icmp ne i32 %tmp3, 168296448 ; <i1> [#uses=1]
%tmp5 = and i1 %tmp2, %tmp4 ; <i1> [#uses=1]
%tmp6 = and i32 %tmp, -256 ; <i32> [#uses=2]
%tmp7 = icmp eq i32 %tmp6, 168296704 ; <i1> [#uses=1]
%tmp8 = icmp eq i32 %tmp3, 168296448 ; <i1> [#uses=2]
%tmp9 = icmp ne i32 %tmp6, 168296704 ; <i1> [#uses=1]
%tmp10 = and i1 %tmp8, %tmp9 ; <i1> [#uses=1]
%tmp11 = load i32* @src-ip ; <i32> [#uses=1]
%tmp12 = and...
2008 Apr 21
3
[LLVMdev] Whole-function isel
...:
switch i32 %x, label %UnifiedReturnBlock [
i32 0, label %bb
i32 1, label %bb5
]
bb: ; preds = %entry
%tmp4 = mul i32 %z, %x ; <i32> [#uses=1]
ret i32 %tmp4
bb5: ; preds = %entry
%tmp8 = add i32 %z, %x ; <i32> [#uses=1]
ret i32 %tmp8
UnifiedReturnBlock: ; preds = %entry
ret i32 %z
}
And here's the X86 DAG right before it gets fed one BB at a time into
pre-RA scheduling. Each color is a different basic block.
Cheers!
--
Chris
-...
2008 Jan 06
2
[LLVMdev] trouble with getelementptr
...;
<i8*> [#uses=1]
%tmp3 = call i32 @puts( i8* %tmp2 ) ; <i32> [#uses=0]
%tmp5 = getelementptr [9 x i8]* @.str4, i64 0, i64 0 ;
<i8*> [#uses=1]
%tmp6 = call i32 @puts( i8* %tmp5 ) ; <i32> [#uses=0]
%tmp8 = getelementptr [7 x i8]* @.str7, i64 0, i64 0 ;
<i8*> [#uses=1]
%tmp9 = call i32 @puts( i8* %tmp8 ) ; <i32> [#uses=0]
ret i32 0
}
;end
llvm-as test.ll -o test.ll.bc
llc test.ll.bc -o test.ll.s
gcc test.ll.s -o test.ll.native
After running a se...
2011 Feb 22
2
[LLVMdev] Clone a function and change signature
...t; [#uses=1]
%tmp5 = sext i16 %tmp4 to i32, !dbg !1024 ; <i32> [#uses=1]
store i32 %tmp5, i32* %yy, align 4, !dbg !1024
%tmp6 = load %struct.MT** @mt, align 8, !dbg !1025 ; <%struct.MT*>
[#uses=1]
call void @MTPoint_DIRECT(%struct.MT* %tmp6, i32* %xx, i32* %yy) nounwind
%tmp8 = load i32* %xx, align 4, !dbg !1026 ; <i32> [#uses=1]
%tmp9 = trunc i32 %tmp8 to i16, !dbg !1026 ; <i16> [#uses=1]
store i16 %tmp9, i16* %x, align 2, !dbg !1026
%tmp10 = load i32* %yy, align 4, !dbg !1027 ; <i32> [#uses=1]
%tmp11 = trunc i32 %tmp10 to i16, !...
2015 Jun 11
4
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
...float* %tmp3, align 16, !tbaa !2
> %tmp5 = getelementptr inbounds [1024 x float], [1024 x float]* @y,
> i64 0, i64 %k.01
> %tmp6 = load float, float* %tmp5, align 8, !tbaa !2
> %tmp7 = fadd float %tmp4, %tmp6
> store float %tmp7, float* %tmp3, align 16, !tbaa !2
> %tmp8 = or i64 %k.01, 1
> %tmp9 = shl nsw i64 %tmp8, 1
> %tmp10 = getelementptr inbounds [1024 x float], [1024 x float]*
> @x, i64 0, i64 %tmp9
> %tmp11 = load float, float* %tmp10, align 8, !tbaa !2
> %tmp12 = getelementptr inbounds [1024 x float], [1024 x float]*
> @y, i64...
2015 Jun 10
3
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
I am testing vectorization on the following test case:
float x[1024], y[1024];
void myloop1() {
for (long int k = 0; k < 512; k++) {
x[2*k] = x[2*k]+y[k];
}
}
Vectorization failed due to "unsafe dependent memory operation". I traced
the LoopAccessAnalysis.cpp and found the reason is the NoWrapFlag for
SCEVAddRecExpr is not set and consequently the
2008 Apr 22
0
[LLVMdev] Whole-function isel
...bel %UnifiedReturnBlock [
> i32 0, label %bb
> i32 1, label %bb5
> ]
> bb: ; preds = %entry
> %tmp4 = mul i32 %z, %x ; <i32> [#uses=1]
> ret i32 %tmp4
> bb5: ; preds = %entry
> %tmp8 = add i32 %z, %x ; <i32> [#uses=1]
> ret i32 %tmp8
> UnifiedReturnBlock: ; preds = %entry
> ret i32 %z
> }
>
> And here's the X86 DAG right before it gets fed one BB at a time
> into pre-RA scheduling. Each color is a different bas...
2007 Jun 12
3
[LLVMdev] ARM backend problem ?
..., ...)
define i32 @main (){
entry:
%n = alloca i32
%f = alloca i32
%i = alloca i32
%zero = alloca i32
%inc = alloca i32
store i32 5, i32* %n
store i32 1, i32* %f
store i32 1, i32* %i
store i32 0 , i32* %zero
store i32 1 , i32* %inc
%tmp7 = load i32* %n
%tmp8 = load i32* %zero
%tmp6 = icmp sgt i32 %tmp7, %tmp8
br i1 %tmp6, label %then4, label %else12
then4:
%tmp14 = load i32* %i
%tmp16 = load i32* %n
%tmp18 = load i32* %inc
%tmp15 = add i32 %tmp16, %tmp18
%tmp13 = icmp slt i32 %tmp14, %tmp15
br i1 %tmp13, label %then11, label...
2013 Oct 27
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
...ne i32 @get32Bits(i8* inreg nocapture readonly %x_arg) #0 {
%tmp1 = getelementptr inbounds i8* %x_arg, i64 3
%tmp2 = load i8* %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
%tmp4 = shl nuw nsw i32 %tmp3, 24
%tmp6 = getelementptr inbounds i8* %x_arg, i64 2
%tmp7 = load i8* %tmp6, align 1
%tmp8 = zext i8 %tmp7 to i32
%tmp9 = shl nuw nsw i32 %tmp8, 16
%tmp10 = or i32 %tmp9, %tmp4
%tmp12 = getelementptr inbounds i8* %x_arg, i64 1
%tmp13 = load i8* %tmp12, align 1
%tmp14 = zext i8 %tmp13 to i32
%tmp15 = shl nuw nsw i32 %tmp14, 8
%tmp16 = or i32 %tmp10, %tmp15
%tmp19 = load i8...
2012 Feb 27
2
[LLVMdev] Alias in LLVM 3.0
...uffle(float2, uint2);
In LLVM 2.9 and LLVM 3.0, our front-end generates:
@__shuffle_2f32_2u32 = alias weak <2 x i32> (<2 x i32>, <2 x i32>)* @4
And the calls, before linking, look like:
%call9 = call <2 x float> @__shuffle_2f32_2u32(<2 x float> %tmp7, <2 x i32> %tmp8) nounwind
After linking with LLVM 3.0, the call looks like:
%call9 = call <2 x float> bitcast (<2 x i32> (<2 x i32>, <2 x i32>)* @__shuffle_2f32_2u32 to <2 x float> (<2 x float>, <2 x i32>)*)(<2 x float> %tmp7, <2 x i32> %tmp8) nounwind
LLVM 3.0...
2007 Jun 12
0
[LLVMdev] ARM backend problem ?
...alloca i32
>
> %zero = alloca i32
>
> %inc = alloca i32
>
> store i32 5, i32* %n
>
> store i32 1, i32* %f
>
> store i32 1, i32* %i
>
> store i32 0 , i32* %zero
>
> store i32 1 , i32* %inc
>
>
>
> %tmp7 = load i32* %n
>
> %tmp8 = load i32* %zero
>
> %tmp6 = icmp sgt i32 %tmp7, %tmp8
>
> br i1 %tmp6, label %then4, label %else12
>
>
>
> then4:
>
> %tmp14 = load i32* %i
>
> %tmp16 = load i32* %n
>
> %tmp18 = load i32* %inc
>
> %tmp15 = add i32 %tmp16, %tmp18
>
&g...
2008 Jan 04
0
[LLVMdev] Extraction of Arguments Passed to a Function
...for different basic block are independent from each other, for example in
the following IR the temp variables used in the basic block bb: i.e. %tmp,
%tmp1, %tmp2 are only dependent on the variables defined in the entry: basic
block, and same holds for basic block bb5: i.e. variables %tmp6, %tmp7,
%tmp8 etc are only dependent on the variables in the entry block
(%limit_addr, %i.. etc) and the temp variables defined in the same basic
block.
Is this true ?, as far as i have seen, by generating the bitcode for various
test codes, and it holds true for all. So, now the proposition is, that one
can cr...
2008 Dec 09
1
[LLVMdev] scalar-evolution + indvars fail to get the loop trip count?
...eds = %bb, %entry
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ;
<i32> [#uses=4]
%i.0.reg2mem.0 = sub i32 255, %indvar ; <i32> [#uses=2]
%tmp7 = getelementptr i32* %alp, i32 %i.0.reg2mem.0 ;
<i32*> [#uses=1]
%tmp8 = load i32* %tmp7, align 4 ; <i32> [#uses=1]
%tmp11 = getelementptr i32* %lam, i32 %i.0.reg2mem.0 ;
<i32*> [#uses=1]
store i32 %tmp8, i32* %tmp11, align 4
%tmp13 = sub i32 254, %indvar ; <i32> [#uses=1]
%tmp16 = i...
2011 Feb 22
0
[LLVMdev] Clone a function and change signature
...%tmp4 to i32, !dbg !1024 ; <i32> [#uses=1]
> store i32 %tmp5, i32* %yy, align 4, !dbg !1024
> %tmp6 = load %struct.MT** @mt, align 8, !dbg !1025 ; <%struct.MT*>
> [#uses=1]
> call void @MTPoint_DIRECT(%struct.MT* %tmp6, i32* %xx, i32* %yy)
> nounwind
> %tmp8 = load i32* %xx, align 4, !dbg !1026 ; <i32> [#uses=1]
> %tmp9 = trunc i32 %tmp8 to i16, !dbg !1026 ; <i16> [#uses=1]
> store i16 %tmp9, i16* %x, align 2, !dbg !1026
> %tmp10 = load i32* %yy, align 4, !dbg !1027 ; <i32> [#uses=1]
> %tmp11 = trunc...
2010 Nov 23
1
[LLVMdev] Unrolling loops into constant-time expressions
...; preds = %0
%tmp4 = add i32 %x, -1
%tmp6 = add i32 %x, -2
%tmp16 = add i32 %x, -3
%tmp7 = zext i32 %tmp6 to i33
%tmp5 = zext i32 %tmp4 to i33
%tmp17 = zext i32 %tmp16 to i33
%tmp15 = mul i33 %tmp5, %tmp7
%tmp18 = mul i33 %tmp15, %tmp17
%tmp8 = mul i32 %tmp4, %tmp6
%tmp19 = lshr i33 %tmp18, 1
%2 = shl i32 %tmp8, 2
%tmp20 = trunc i33 %tmp19 to i32
%tmp12 = mul i32 %x, 5
%tmp1125 = and i32 %2, -8
%tmp21 = mul i32 %tmp20, 1431655764
%tmp13 = add i32 %tmp1125, %tmp12
%tmp14 = add i32 %tmp13, -4
%tmp22 = s...
2010 Jan 25
0
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
Hi Ralf,
> I do not understand why this behaviour is required. What is the problem
> in having a function receive a single struct-parameter with three floats
> compared to two scalar parameters?
>
> source-code (C++):
> struct Test3Float { float a, b, c; };
> void test(Test3Float param, Test3Float* result) { ... }
if you compile this with GCC, you will see that it too
2010 Jan 25
2
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
Uh, sorry, did not pay attention where I was replying ;)
Hey Duncan,
I do not understand why this behaviour is required. What is the problem
in having a function receive a single struct-parameter with three floats
compared to two scalar parameters?
source-code (C++):
struct Test3Float { float a, b, c; };
void test(Test3Float param, Test3Float* result) { ... }
bitcode:
2015 Apr 28
2
[LLVMdev] alias set collapse and LICM
On Mon, Apr 27, 2015 at 4:21 PM, Daniel Berlin <dberlin at dberlin.org> wrote:
> You can't win here (believe me, i've tried, and better people than me have
> tried, for years :P).
> No matter what you do, the partitioning will never be 100% precise. The
> only way to solve that in general is to pairwise query over the
> partitioning.
>
> Your basic problem is