search for: tmp6

Displaying 20 results from an estimated 91 matches for "tmp6".

Did you mean: tmp
2006 Jul 23
3
RfW 2.3.1: regular expressions to detect pairs of identical word-final character sequences
Dear all I use R for Windows 2.3.1 on a fully updated Windows XP Home SP2 machine and I have two related regular expression problems. platform i386-pc-mingw32 arch i386 os mingw32 system i386, mingw32 status major 2 minor
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
...=1] %tmp2 = icmp eq i32 %tmp1, 167772160 ; <i1> [#uses=2] %tmp3 = and i32 %tmp, -65536 ; <i32> [#uses=2] %tmp4 = icmp ne i32 %tmp3, 168296448 ; <i1> [#uses=1] %tmp5 = and i1 %tmp2, %tmp4 ; <i1> [#uses=1] %tmp6 = and i32 %tmp, -256 ; <i32> [#uses=2] %tmp7 = icmp eq i32 %tmp6, 168296704 ; <i1> [#uses=1] %tmp8 = icmp eq i32 %tmp3, 168296448 ; <i1> [#uses=2] %tmp9 = icmp ne i32 %tmp6, 168296704 ; <i1> [#uses=1] %tmp10 = and...
2008 May 02
4
[LLVMdev] Pointer sizes, GetElementPtr, and offset sizes
...; <[2 x i32*]*> [#uses=2] %tmp1 = getelementptr [2 x i32*]* %x, i32 0, i32 1 ; <i32**> [#uses=1] %tmp23 = ptrtoint i32** %tmp1 to i32 ; <i32> [#uses=1] %x45 = ptrtoint [2 x i32*]* %x to i32 ; <i32> [#uses=1] %tmp6 = sub i32 %tmp23, %x45 ; <i32> [#uses=1] %tmp7 = ashr i32 %tmp6, 2 ; <i32> [#uses=1] ret i32 %tmp7 } The return value is 1. The ashr exposes the pointer size by shifting the 4 byte distance over by 2. For the analysis that I am doing, it would...
2011 Jul 17
0
[LLVMdev] Trying to optimize out store/load pair
...32* %gVal, align 4, !tbaa !2 store i32 %shr47.i197, i32* %bVal, align 4, !tbaa !2 store i32 %threadSliceNum, i32* %threadID, align 4, !tbaa !2 %.idx.val.i = load i32* %.idx.i, align 4, !tbaa !2 %arrayidx.i.i.i = getelementptr inbounds i32* inttoptr (i32 33807872 to i32*), i32 %.idx.val.i %tmp6.i.i.i = load i32* %arrayidx.i.i.i, align 4, !tbaa !2 %inc.i.i.i = add i32 %tmp6.i.i.i, 1 store i32 %inc.i.i.i, i32* %arrayidx.i.i.i, align 4, !tbaa !2 %arrayidx.i.i6.i = getelementptr inbounds i32* inttoptr (i32 33812992 to i32*), i32 %.idx.val.i %tmp6.i.i7.i = load i32* %arrayidx.i.i6.i, a...
2010 Nov 23
1
[LLVMdev] Unrolling loops into constant-time expressions
...0; i < x; i++) { ret += 1+i*i + i*(i+2); } return ret; } generates: define i32 @loop(i32 %x) nounwind readnone { %1 = icmp sgt i32 %x, 0 br i1 %1, label %bb.nph, label %3 bb.nph: ; preds = %0 %tmp4 = add i32 %x, -1 %tmp6 = add i32 %x, -2 %tmp16 = add i32 %x, -3 %tmp7 = zext i32 %tmp6 to i33 %tmp5 = zext i32 %tmp4 to i33 %tmp17 = zext i32 %tmp16 to i33 %tmp15 = mul i33 %tmp5, %tmp7 %tmp18 = mul i33 %tmp15, %tmp17 %tmp8 = mul i32 %tmp4, %tmp6 %tmp19 = lshr i33 %tmp18, 1 %2 = shl i3...
2011 Jul 17
0
[LLVMdev] Trying to optimize out store/load pair
...store i32 %threadSliceNum, i32* %threadID, align 4, !tbaa !2 %.idx.val.i = load i32* %.idx.i, align 4, !tbaa !2 /// and this load replaced by the original reg (%shr47.i197 above) %arrayidx.i.i.i = getelementptr inbounds i32* inttoptr (i32 33807872 to i32*), i32 %.idx.val.i %tmp6.i.i.i = load i32* %arrayidx.i.i.i, align 4, !tbaa !2 %inc.i.i.i = add i32 %tmp6.i.i.i, 1 store i32 %inc.i.i.i, i32* %arrayidx.i.i.i, align 4, !tbaa !2 %arrayidx.i.i6.i = getelementptr inbounds i32* inttoptr (i32 33812992 to i32*), i32 %.idx.val.i %tmp6.i.i7.i = load i32* %arrayidx.i.i6.i, align...
2011 Feb 22
2
[LLVMdev] Clone a function and change signature
...2 to i32, !dbg !1023 ; <i32> [#uses=1] store i32 %tmp3, i32* %xx, align 4, !dbg !1023 %tmp4 = load i16* %y, align 2, !dbg !1024 ; <i16> [#uses=1] %tmp5 = sext i16 %tmp4 to i32, !dbg !1024 ; <i32> [#uses=1] store i32 %tmp5, i32* %yy, align 4, !dbg !1024 %tmp6 = load %struct.MT** @mt, align 8, !dbg !1025 ; <%struct.MT*> [#uses=1] call void @MTPoint_DIRECT(%struct.MT* %tmp6, i32* %xx, i32* %yy) nounwind %tmp8 = load i32* %xx, align 4, !dbg !1026 ; <i32> [#uses=1] %tmp9 = trunc i32 %tmp8 to i16, !dbg !1026 ; <i16> [#uses=1...
2008 Jan 12
1
[LLVMdev] Labels
...pos, align 4 %tmp1044 = sub i32 %tmp842, %tmp943 %tmp1145 = icmp slt i32 %tmp1044, 512 br i1 %tmp1145, label %bb, label %bb13 bb: %tmp2.rle = phi i32 [ %tmp842, %entry ], [ %tmp8, %bb ] %tmp3 = shl i32 %tmp2.rle, 1 store i32 %tmp3, i32* @yybuflen, align 4 %tmp5 = load i8** @yybuf, align 4 %tmp6 = tail call i8* @realloc( i8* %tmp5, i32 %tmp3 ) store i8* %tmp6, i8** @yybuf, align 4 %tmp8 = load i32* @yybuflen, align 4 %tmp9 = load i32* @yypos, align 4 %tmp10 = sub i32 %tmp8, %tmp9 %tmp11 = icmp slt i32 %tmp10, 512 br i1 %tmp11, label %bb, label %bb13 bb13: %tmp15 = load %struct._IO_...
2011 Apr 05
3
[LLVMdev] Incompatible types at call site
Hi, For a call like this, %tmp6 = call i32 (...)* bitcast (i32 (i8*, i8, i8**)* @ssplit to i32 (...)*)(i8* %tmp599, i32 46, i8** %domainv3) nounwind ; <i32> does the 2nd argument get zero extended or sign extended? Thanks, Arushi -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://li...
2016 Jan 15
2
[GlobalISel][RFC] Value to vreg during IR to MachineInstr translation for aggregate type
...b, struct bar *addr) { struct bar tmp; tmp.a = a; tmp.b = b; *addr = tmp; } * Solution A: Replicate SDAG * Note: (#) is the size of the virtual register. - Translation: arg1(32) = copy R0 arg2(32) = copy R1 addr(32) = copy R2 a(16) = truncate arg1(32) b(16) = truncate arg2(32) tmp5(16), tmp6(16) = merge_value a(16), b(16) store tmp5(16), addr(32), 0 store tmp6(16), addr(32), 4 - Legalization: arg1(32) = copy R0 arg2(32) = copy R1 addr(32) = copy R2 tmp5(16) = extract_subreg a(32), 0 tmp6(16) = extract_subreg b(32), 0 store tmp5(16), addr(32), 0 store tmp6(16), addr(32), 4 * Solution...
2008 May 02
0
[LLVMdev] Pointer sizes, GetElementPtr, and offset sizes
...2*] ; <[2 x i32*]*> [#uses=2] %tmp1 = getelementptr [2 x i32*]* %x, i32 0, i32 1 ; <i32**> [#uses=1] %tmp23 = ptrtoint i32** %tmp1 to i32 ; <i32> [#uses=1] %x45 = ptrtoint [2 x i32*]* %x to i32 ; <i32> [#uses=1] %tmp6 = sub i32 %tmp23, %x45 ; <i32> [#uses=1] %size = getelementptr i32** null, i32 1 ; <i32**> [#uses=1] %sizeI = ptrtoint i32** %size to i32 ; <i32> [#uses=1] %tmp7 = ashr i32 %tmp6, %sizeI ; <i32> [#uses=1]...
2011 Jan 04
2
Print plot to pdf, jpg or any other format when using scatter3d error
...ionID == sessionU01[i,],select=c(timelineMSEC,X,Y)) userSubset x<-as.numeric(userSubset$X) y<-as.numeric(userSubset$Y) scatter3d(x,y,userSubset$timeline,xlim = c(0,1280), ylim = c(0,1024), zlim=c(0,1800000),type="h",main=sessionU01[i,],sub=sessionU01[i,]) tmp6=rep(".ps") tmp7=paste(sessionU01[i,],tmp6,sep="") tmp7 rgl.postscript(tmp7,"ps",drawText=FALSE) #pdf(file=tmp7) #dev.print(file=tmp7, device=pdf, width=600) #dev.off(2) }
2010 Sep 29
0
[LLVMdev] spilling & xmm register usage
...> entry.header.loop.end: ; preds = %cond.then.i201.i, %phi.exit138.i > %cond.i204.i = phi float [ %tmp43.i200.i, %cond.then.i201.i ], [ %tmp38.i194.i, %phi.exit138.i ] > %arrayidx82.i = getelementptr float addrspace(1)* %5, i64 %8 > %tmp85.i = fmul float %tmp63.i, %cond.i204.i > %tmp88.i = fmul float %tmp9.i, %cond.i135.i > %tmp89.i = fsub float %tmp85.i, %tmp88.i > store float %tmp89.i, float addrspace(1)* %arrayidx82.i, align 4 > %inc = add i32 %7, 1 > %exitcond = icmp eq i32 %inc, %local_size_0 > br i1 %exitcond, label %exit, l...
2007 Jun 12
3
[LLVMdev] ARM backend problem ?
...(){ entry: %n = alloca i32 %f = alloca i32 %i = alloca i32 %zero = alloca i32 %inc = alloca i32 store i32 5, i32* %n store i32 1, i32* %f store i32 1, i32* %i store i32 0 , i32* %zero store i32 1 , i32* %inc %tmp7 = load i32* %n %tmp8 = load i32* %zero %tmp6 = icmp sgt i32 %tmp7, %tmp8 br i1 %tmp6, label %then4, label %else12 then4: %tmp14 = load i32* %i %tmp16 = load i32* %n %tmp18 = load i32* %inc %tmp15 = add i32 %tmp16, %tmp18 %tmp13 = icmp slt i32 %tmp14, %tmp15 br i1 %tmp13, label %then11, label %else12 then11: %tm...
2008 Jan 06
4
[LLVMdev] Another memory fun
...k: %.str3 = getelementptr [8 x i8]* @.str2, i64 0, i64 0 ; <i8*> [#uses=1] %.str4 = getelementptr [8 x i8]* @.str1, i64 0, i64 0 ; <i8*> [#uses=1] %tmp5 = call i8* @strcat( i8* %.str3, i8* %.str4 ) ; <i8*> [#uses=1] %tmp6 = call i32 @puts( i8* %tmp5 ) ; <i32> [#uses=0] %.str8 = getelementptr [21 x i8]* @.str7, i64 0, i64 0 ; <i8*> [#uses=1] %tmp9 = call i32 @puts( i8* %.str8 ) ; <i32> [#uses=0] ret i32 0 } After compilation I see next(without...
2010 Sep 29
3
[LLVMdev] spilling & xmm register usage
Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under
2013 Oct 27
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
...iple = "x86_64-unknown-linux-gnu" ; Function Attrs: nounwind readonly define i32 @get32Bits(i8* inreg nocapture readonly %x_arg) #0 { %tmp1 = getelementptr inbounds i8* %x_arg, i64 3 %tmp2 = load i8* %tmp1, align 1 %tmp3 = zext i8 %tmp2 to i32 %tmp4 = shl nuw nsw i32 %tmp3, 24 %tmp6 = getelementptr inbounds i8* %x_arg, i64 2 %tmp7 = load i8* %tmp6, align 1 %tmp8 = zext i8 %tmp7 to i32 %tmp9 = shl nuw nsw i32 %tmp8, 16 %tmp10 = or i32 %tmp9, %tmp4 %tmp12 = getelementptr inbounds i8* %x_arg, i64 1 %tmp13 = load i8* %tmp12, align 1 %tmp14 = zext i8 %tmp13 to i32 %...
2016 Jan 15
2
[GlobalISel][RFC] Value to vreg during IR to MachineInstr translation for aggregate type
...: (#) is the size of the virtual register. >> >> >> - Translation: >> >> >> >> >> arg1(32) = copy R0 >> arg2(32) = copy R1 >> addr(32) = copy R2 >> a(16) = truncate arg1(32) >> b(16) = truncate arg2(32) >> tmp5(16), tmp6(16) = merge_value a(16), b(16) >> store tmp5(16), addr(32), 0 >> store tmp6(16), addr(32), 4 >> >> >> - Legalization: >> >> >> >> arg1(32) = copy R0 >> arg2(32) = copy R1 >> addr(32) = copy R2 >> tmp5(16) = extract_subreg...
2017 Apr 28
3
Store unswitch
...nicity of heuristic* What I'm trying to say here is the greedy algorithms work best when the heuristic they are computing is monotonic. Consider this: if (a) { tmp1 = *b; tmp2 = *c; tmp3 = tmp1 + tmp2; *d = tmp3; } else { tmp4 = *b; tmp5 = *c; tmp6 = tmp4 + tmp5; *e = tmp6; } If we proceed sequentially from the bottom of these blocks, trying to determine if sinking them is worthwhile: Step 1: [*e = tmp6], [*d = tmp3] - This is the same operation, a store, but it requires two PHIs - one for (e,d) and one for (tmp6, tmp3). - Thi...
2017 Mar 30
2
InstructionSimplify: adding a hook for shufflevector instructions
Thanks, Sanjay, that makes sense. The opportunity for improving instcombining splat sounds promising. Another question about shuffle simplification. This is a testcase from test/Transforms/InstCombine/vec_shuffle.ll: define <4 x i32> @test10(<4 x i32> %tmp5) nounwind { %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %tmp7 = shufflevector <4 x i32> %tmp6, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %tmp7 } opt –instcombine will combine to: defin...