search for: tmp5

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2017 Mar 30
2
InstructionSimplify: adding a hook for shufflevector instructions
Thanks, Sanjay, that makes sense. The opportunity for improving instcombining splat sounds promising. Another question about shuffle simplification. This is a testcase from test/Transforms/InstCombine/vec_shuffle.ll: define <4 x i32> @test10(<4 x i32> %tmp5) nounwind { %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %tmp7 = shufflevector <4 x i32> %tmp6, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %tmp7 } opt –instcombine w...
2007 Nov 23
1
[LLVMdev] Will any pass change simple return branch into select/return pair?
Hi, Can any llvm pass change simple return branch into select/return pair? For example: define i10 @mod_N(i10 zeroext %a) zeroext { entry: %tmp2 = icmp ugt i10 %a, -400 ; <i1> [#uses=1] br i1 %tmp2, label %cond_true, label %return cond_true: ; preds = %entry %tmp5 = add i10 %a, 400 ; <i10> [#uses=1] ret i10 %tmp5 return: ; preds = %entry ret i10 %a } Changed into: define i10 @mod_N(i10 zeroext %a) zeroext { entry: %tmp2 = icmp ugt i10 %a, -400 ; <i1> [#uses=1] %tmp5 = add i10 %a, 400 ; <i10> [#uses=1]...
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
...3] %tmp1 = and i32 %tmp, -16777216 ; <i32> [#uses=1] %tmp2 = icmp eq i32 %tmp1, 167772160 ; <i1> [#uses=2] %tmp3 = and i32 %tmp, -65536 ; <i32> [#uses=2] %tmp4 = icmp ne i32 %tmp3, 168296448 ; <i1> [#uses=1] %tmp5 = and i1 %tmp2, %tmp4 ; <i1> [#uses=1] %tmp6 = and i32 %tmp, -256 ; <i32> [#uses=2] %tmp7 = icmp eq i32 %tmp6, 168296704 ; <i1> [#uses=1] %tmp8 = icmp eq i32 %tmp3, 168296448 ; <i1> [#uses=2] %tmp9 = icmp...
2008 Jan 06
4
[LLVMdev] Another memory fun
...rcat(i8*, i8*) declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) define i32 @main() { mainBlock: %.str3 = getelementptr [8 x i8]* @.str2, i64 0, i64 0 ; <i8*> [#uses=1] %.str4 = getelementptr [8 x i8]* @.str1, i64 0, i64 0 ; <i8*> [#uses=1] %tmp5 = call i8* @strcat( i8* %.str3, i8* %.str4 ) ; <i8*> [#uses=1] %tmp6 = call i32 @puts( i8* %tmp5 ) ; <i32> [#uses=0] %.str8 = getelementptr [21 x i8]* @.str7, i64 0, i64 0 ; <i8*> [#uses=1] %tmp9 = call i32 @puts( i8* %.str...
2007 Oct 16
1
[LLVMdev] one remaining CellSPU backend bug...
...%tmp1 = load i8** getelementptr ([0 x i8*]* @__JCR_LIST__, i32 0, i32 0), align 4 ; <i8*> [#uses=1] %tmp2 = icmp eq i8* %tmp1, null ; <i1> [#uses=1] br i1 %tmp2, label %UnifiedReturnBlock, label %bb bb: ; preds = %entry %tmp5 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0"( void (i8*)* @_Jv_RegisterClasses ) ; <void (i8*)*> [#uses=2] %tmp7 = icmp eq void (i8*)* %tmp5, null ; <i1> [#uses=1] br i1 %tmp7, label %UnifiedReturnBlock, label %bb10 bb10:...
2010 Sep 29
0
[LLVMdev] spilling & xmm register usage
...%entry.header.loop.end > %7 = phi i32 [ %inc, %entry.header.loop.end ], [ 0, %entry ] > %global_id_0 = add i32 %7, %6 > %8 = sext i32 %global_id_0 to i64 > %arrayidx.i = getelementptr float addrspace(1)* %1, i64 %8 > %tmp3.i = load float addrspace(1)* %arrayidx.i, align 4 > %tmp5.i = fmul float %tmp3.i, 1.000000e+01 > %tmp7.i = fsub float 1.000000e+00, %tmp3.i > %tmp8.i = fmul float %tmp7.i, 1.000000e+02 > %tmp9.i = fadd float %tmp5.i, %tmp8.i > %tmp20.i = fmul float %tmp7.i, 1.000000e+01 > %tmp21.i = fadd float %tmp3.i, %tmp20.i > %tmp23.i = fmul fl...
2008 Jan 06
2
[LLVMdev] trouble with getelementptr
...<[7 x i8]*> [#uses=1] declare i32 @puts(i8*) declare i8 @strcat(i8*, i8*) define i32 @main() { mainBlock: %tmp2 = getelementptr [20 x i8]* @.str1, i64 0, i64 0 ; <i8*> [#uses=1] %tmp3 = call i32 @puts( i8* %tmp2 ) ; <i32> [#uses=0] %tmp5 = getelementptr [9 x i8]* @.str4, i64 0, i64 0 ; <i8*> [#uses=1] %tmp6 = call i32 @puts( i8* %tmp5 ) ; <i32> [#uses=0] %tmp8 = getelementptr [7 x i8]* @.str7, i64 0, i64 0 ; <i8*> [#uses=1] %tmp9 = call i32 @puts( i8* %tmp8...
2010 Sep 29
3
[LLVMdev] spilling & xmm register usage
Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under
2011 Feb 22
2
[LLVMdev] Clone a function and change signature
...; preds = %entry %tmp2 = load i16* %x, align 2, !dbg !1023 ; <i16> [#uses=1] %tmp3 = sext i16 %tmp2 to i32, !dbg !1023 ; <i32> [#uses=1] store i32 %tmp3, i32* %xx, align 4, !dbg !1023 %tmp4 = load i16* %y, align 2, !dbg !1024 ; <i16> [#uses=1] %tmp5 = sext i16 %tmp4 to i32, !dbg !1024 ; <i32> [#uses=1] store i32 %tmp5, i32* %yy, align 4, !dbg !1024 %tmp6 = load %struct.MT** @mt, align 8, !dbg !1025 ; <%struct.MT*> [#uses=1] call void @MTPoint_DIRECT(%struct.MT* %tmp6, i32* %xx, i32* %yy) nounwind %tmp8 = load i32* %xx...
2016 Jan 15
2
[GlobalISel][RFC] Value to vreg during IR to MachineInstr translation for aggregate type
...a, short b, struct bar *addr) { struct bar tmp; tmp.a = a; tmp.b = b; *addr = tmp; } * Solution A: Replicate SDAG * Note: (#) is the size of the virtual register. - Translation: arg1(32) = copy R0 arg2(32) = copy R1 addr(32) = copy R2 a(16) = truncate arg1(32) b(16) = truncate arg2(32) tmp5(16), tmp6(16) = merge_value a(16), b(16) store tmp5(16), addr(32), 0 store tmp6(16), addr(32), 4 - Legalization: arg1(32) = copy R0 arg2(32) = copy R1 addr(32) = copy R2 tmp5(16) = extract_subreg a(32), 0 tmp6(16) = extract_subreg b(32), 0 store tmp5(16), addr(32), 0 store tmp6(16), addr(32), 4...
2008 Jan 12
1
[LLVMdev] Labels
...n, align 4 %tmp943 = load i32* @yypos, align 4 %tmp1044 = sub i32 %tmp842, %tmp943 %tmp1145 = icmp slt i32 %tmp1044, 512 br i1 %tmp1145, label %bb, label %bb13 bb: %tmp2.rle = phi i32 [ %tmp842, %entry ], [ %tmp8, %bb ] %tmp3 = shl i32 %tmp2.rle, 1 store i32 %tmp3, i32* @yybuflen, align 4 %tmp5 = load i8** @yybuf, align 4 %tmp6 = tail call i8* @realloc( i8* %tmp5, i32 %tmp3 ) store i8* %tmp6, i8** @yybuf, align 4 %tmp8 = load i32* @yybuflen, align 4 %tmp9 = load i32* @yypos, align 4 %tmp10 = sub i32 %tmp8, %tmp9 %tmp11 = icmp slt i32 %tmp10, 512 br i1 %tmp11, label %bb, label %bb13...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...tmp1sign = icmp slt <4 x i32> %tmp1, zeroinitializer %sumsign = icmp slt <4 x i32> %tmp2, zeroinitializer %signsequal = icmp eq <4 x i1> %tmpsign, %tmp1sign %summismatch = icmp ne <4 x i1> %sumsign, %tmpsign %overflow = and <4 x i1> %signsequal, %summismatch %tmp5 = bitcast <4 x i1> %overflow to i4 %tmp6 = icmp ne i4 %tmp5, 0 br i1 %tmp6, label %OverflowFail, label %OverflowOk OverflowFail: ; preds = %Entry tail call fastcc void @panic() unreachable OverflowOk: ; preds...
2009 Nov 11
3
[LLVMdev] Puzzled by results of -O3
...oca [1024 x i32], align 4 ; <[1024 x i32]*> [#uses=2] %tmp3 = getelementptr inbounds [1024 x i32]* %tmp, i32 0, i32 0 ; <i32*> [#uses=1] %tmp4 = bitcast [1024 x i32]* %tmp to [1 x i32]* ; <[1 x i32]*> [#uses=1] store [1 x i32] zeroinitializer, [1 x i32]* %tmp4 %tmp5 = load i32* %tmp3 ; <i32> [#uses=1] ret i32 %tmp5 } --- %tmp is what I'd like to call a local heap: It is allocated in the entry function and passed as a parameter to all called functions. These functions can then perform instantiations of types with reference...
2007 Sep 19
2
By() with method = spearman
...hod='pearson') However, this generates an error by(tmp[,c('mtsc07', 'DCBASmathscoreSPRING')], tmp$Grade, cor, use='complete', method='spearman') Error in FUN(data[x, ], ...) : 'x' is empty I can subset the data by grade and compute spearman rho as tmp5 <- subset(tmp, Grade == 5) cor(tmp5[,c('mtsc07', 'DCBASmathcountSPRING')], use='complete', method='spearman') But doing this iteratively is inefficient. I don't see anything in the help man for by() or cor() that tells me what the problem is. I might be miss...
2008 Jun 11
4
[LLVMdev] Query on optimization and tail call.
...t computes the sum as n*(n+1)/2. However, when I try just this: int sum(int n) { return n + sum(n-1); } it generates this: define i32 @sum(i32 %n) nounwind { entry: %tmp2 = add i32 %n, -1 ; <i32> [#uses=1] %tmp3 = tail call i32 @sum( i32 %tmp2 ) nounwind ; <i32> [#uses=1] %tmp5 = add i32 %tmp3, %n ; <i32> [#uses=1] ret i32 %tmp5 } Why isn't llvm able to eliminate the tail call in this (simpler) case? Regards, -Mahadevan.
2016 Jan 15
2
[GlobalISel][RFC] Value to vreg during IR to MachineInstr translation for aggregate type
...;> Note: (#) is the size of the virtual register. >> >> >> - Translation: >> >> >> >> >> arg1(32) = copy R0 >> arg2(32) = copy R1 >> addr(32) = copy R2 >> a(16) = truncate arg1(32) >> b(16) = truncate arg2(32) >> tmp5(16), tmp6(16) = merge_value a(16), b(16) >> store tmp5(16), addr(32), 0 >> store tmp6(16), addr(32), 4 >> >> >> - Legalization: >> >> >> >> arg1(32) = copy R0 >> arg2(32) = copy R1 >> addr(32) = copy R2 >> tmp5(16) = extra...
2015 Feb 25
2
[LLVMdev] [lld][PECOFF] assert from lld once in 5 test runs.
..._start_main /build/buildd/eglibc-2.15/csu/libc-start.c:258:0 #15 0x421d35 _start (/local/mnt/workspace/shankare/work/llvmorg/llvm-build/bin/lld+0x421d35) Stack dump: 0. Program arguments: lld /out:/local/mnt/workspace/shankare/work/llvmorg/llvm-build/tools/lld/test/pecoff/Output/export.test.tmp5.dll /dll /entry:init /export:exportfn7 -- /local/mnt/workspace/shankare/work/llvmorg/llvm-build/tools/lld/test/pecoff/Output/export.test.tmp.obj -flavor link /local/mnt/workspace/shankare/work/llvmorg/llvm-build/tools/lld/test/pecoff/Output/export.test.script: line 18: 16942 Aborted...
2007 Apr 04
0
[LLVMdev] For a small help
...elementptr ([3 x int (...)*]* %vtable for TestClass, int 0, long 2), int (...)*** %tmp %tmp1 = call int %TestClass::testMethod(int)( %struct.TestClass* %obj, int 1 ) ; <int> [#uses=1] %tmp3 = call int %TestClass::testMethod2(int)( %struct.TestClass* %obj, int 1 ) ; <int> [#uses=1] %tmp5 = add int %tmp3, %tmp1 ; <int> [#uses=1] ret int %tmp5 } declare int %TestClass::testMethod(int)(%struct.TestClass*, int) declare int %TestClass::testMethod2(int)(%struct.TestClass*, int) Note the "%vtable for TestClass" external constant array. Hope this helps, Reid. >...
2017 Mar 30
2
InstructionSimplify: adding a hook for shufflevector instructions
As Sanjay noted in D31426<https://reviews.llvm.org/D31426#712701>, InstructionSimplify is missing the following simplification: This function: define <4 x i32> @splat_operand(<4 x i32> %x) { %splat = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer %shuf = shufflevector <4 x i32> %splat, <4 x i32> undef, <4 x i32>
2008 Mar 04
0
[LLVMdev] Deleting Instructions after Intrinsic Creation
...rintf( i8* noalias getelementptr ([15 x i8]* @.str2, i32 0, i32 0) ) nounwind ; <i32> [#uses=0] %tmp4.i = call i32 (i8*, ...)* @scanf( i8* noalias getelementptr ([3 x i8]* @.str3, i32 0, i32 0), i32* %year.i ) nounwind ; <i32> [#uses=0] %tmp5.i = load i32* %year.i, align 4 ; <i32> [#uses=3] %tmp12.i = sitofp i32 %tmp5.i to double ; <double> [#uses=1] %tmp3.i = sub double %tmp12.i, 1.000000e+00 ; <double> [#uses=3] %tmp4.i1 = fdiv double %tmp3.i, 4.000000e+00...