Displaying 5 results from an estimated 5 matches for "tmovr".
Did you mean:
tmov
2014 Aug 20
2
[LLVMdev] ARMv4T Copy Lowering
...namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI), RI(STI) {
}
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tMOVr);
NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
NopInst.addOperand(MCOperand::CreateReg(0));
}
unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
return 0;...
2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
...middle of basic blocks.
I did not expect a branch in the middle of a basic block either, until yesterday LLVM Release 4.0.0 produced the following machine basic block before the pass ARMConstantIslands is run:
bb.1.if.end:
successors: %bb.3.for.body(0x80000000)
liveins: %r4
%r0 = tMOVr %r4, 14, _, debug-location !23
tBL 14, _, $__aeabi_i2d, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp, implicit-def %r0, implicit-def %r1, debug-location !23
tBL 14, _, @sqrt, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implic...
2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
> The right way to update the CFG very much depends on how you're
> transforming it.
I would like to export the CFG for control flow checking.
Theoretically, it should be possible for a compiler to know every target of every control flow instruction, except for computed targets that are not known at compile-time.
When a machine basic block is split between two branches, as shown below:
2015 Aug 10
2
ARM: Predicated returns considered analyzable?
...<kill>, %LR<kill>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
%R7<def> = tMOVr %SP<kill>, pred:14, pred:%noreg; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
t2CMPri %R1<kill>, 0, pred:14, pred:%noreg, %CPSR<imp-def>
t2CMPri %R0<kill>, 3, pred:1, pred:%CPSR, %CPSR<imp-def>,
%CPSR&l...
2015 Jan 11
3
[LLVMdev] [RFC] [PATCH] add tail call optimization to thumb1-only targets
...gState::Kill));
+
+ StackSlotForSavedLR ++;
+ }
+
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
+ .addReg(ARM::R4, RegState::Define)
+ .addReg(ARM::SP)
+ .addImm(StackSlotForSavedLR));
+
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
+ .addReg(ARM::LR, RegState::Define)
+ .addReg(ARM::R4, RegState::Kill));
+ }
+
+ MachineInstrBuilder MIB = BuildMI(MF, dl, TII.get(ARM::tPOP));
+ AddDefaultPred(MIB);
+
+ bool NumRegs = false;
+ for (unsigned i = CSI.size(); i != 0; --i) {
+ unsigned Reg = CSI[i...