Displaying 5 results from an estimated 5 matches for "tmm6".
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tmm0
2020 Aug 24
2
Intel AMX programming model discussion.
...er?
>
> */ MOV row, col info to %stack.0 for each physical tile register
> ??????/*
>
> */ LDTILECFG %stack.0, 1, $noreg, 0, $noreg, implicit-def $tmm0,
> implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3,
> implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6,
> implicit-def $tmm7/*
>
> / $tmm0 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg/
>
> / $tmm1 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg/
>
> / $tmm2 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg/
>
> /$tmm2 = TDPBSSDV $tmm2(tied-def 0), $tmm0, $tm...
2020 Sep 04
2
Intel AMX programming model discussion.
...*/ MOV row, col info to %stack.0 for each physical tile
> register ??????/*
>
> */ LDTILECFG %stack.0, 1, $noreg, 0, $noreg, implicit-def $tmm0,
> implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3,
> implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6,
> implicit-def $tmm7/*
>
> / $tmm0 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg/
>
> / $tmm1 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg/
>
> / $tmm2 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg/
>
> /$tmm2 = TDPBSSDV $tmm2(tied...
2020 Sep 04
2
Intel AMX programming model discussion.
...e know the shape of the physical tile register?
MOV row, col info to %stack.0 for each physical tile register ??????
LDTILECFG %stack.0, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7
$tmm0 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg
$tmm1 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg
$tmm2 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg
$tmm2 = TDPBSSDV $tmm2(tied-def 0), $tmm0, $tmm1
Thanks
Yuanke
...
--
Hal Finkel
Lead, Compiler...
2020 Aug 21
2
Intel AMX programming model discussion.
...e know the shape of the physical tile register?
MOV row, col info to %stack.0 for each physical tile register ??????
LDTILECFG %stack.0, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7
$tmm0 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg
$tmm1 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg
$tmm2 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg
$tmm2 = TDPBSSDV $tmm2(tied-def 0), $tmm0, $tmm1
Thanks
Yuanke
From: Hal Finkel <hfinkel at anl....
2020 Aug 19
3
Intel AMX programming model discussion.
The width and height can be runtime values that we would just copy into 64 byte configuration block we pass to ldtilecfg. So the code doesn't need to be multiversioned. The user code would also use those values to update pointers in the loops they write using the tiles. If we can't determine that two tiles were defined with the same width and height we need to assume the shape is different