search for: tlively

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2019 Nov 20
2
Question about physical registers in ISel
...x SDISel to accept both physical and > virtual definitions on variadic instructions. Though I wouldn’t bother > adding the support for implicit virtual definition. > > I don’t think we need a bit to allow if we go that direction. > > On Nov 19, 2019, at 10:29 AM, Thomas Lively <tlively at google.com> wrote: > > To get into more detail, I'm trying to update WebAssembly's `call` > instruction. `call` is currently constrained to return one or zero > arguments, so in TableGen we have a separate call Instruction for each > possible return type. But I need to...
2020 Jun 30
2
LLVM Incubator + new projects draft
Hah, whoops, sorry about that. This is the correct link: https://docs.google.com/document/d/1ss4jGHywL0Y2KW_l4LqTo5CgJxx3i0_4-FkbXiPQMus/edit <https://docs.google.com/document/d/1ss4jGHywL0Y2KW_l4LqTo5CgJxx3i0_4-FkbXiPQMus/edit> -Chris > On Jun 30, 2020, at 1:41 PM, Thomas Lively <tlively at google.com> wrote: > > Hi Chris, > > I'm also seeing an access denied error on the first link you shared, and although I can access the second document, it doesn't look like the document you meant to share. It looks like a one pager on ML in Swift. > > Thomas >...
2020 Jul 01
6
LLVM Incubator + new projects draft
...ailto:llvm-dev at lists.llvm.org>> wrote: > > Hah, whoops, sorry about that.  This is the correct link: > https://docs.google.com/document/d/1ss4jGHywL0Y2KW_l4LqTo5CgJxx3i0_4-FkbXiPQMus/edit > > -Chris > >> On Jun 30, 2020, at 1:41 PM, Thomas Lively <tlively at google.com >> <mailto:tlively at google.com>> wrote: >> >> Hi Chris, >> >> I'm also seeing an access denied error on the first link you >> shared, and although I can access the second document, it doesn't >> look like...
2019 Nov 19
2
Question about physical registers in ISel
...und a proper modeling. If you want to pursue with that approach, > I would need more information on the semantic of that bit, how it is going > to be used, what problem it solves and so on, to give a better opinion. > > Cheers, > Q > > Le 18 nov. 2019 à 19:35, Thomas Lively <tlively at google.com> a écrit : > >  > Hi Quentin, > > Thanks, that explanation makes sense. I can see that in a normal register > machine, implicitly defs must be physical registers. In a stack machine > like WebAssembly, though, implicit defs are known to be pushed onto the >...
2018 Nov 08
2
Proposed new min and max intrinsics
...ing these operations in terms of existing operations is actually rather complicated. Do you think it would make sense to add builtin functions to compiler-rt to implement these operations, or is there a better way of handling this? Thanks, Thomas On Thu, Nov 1, 2018 at 11:49 AM Thomas Lively <tlively at google.com> wrote: > Sounds good, I'll take a look. > > On Thu, Nov 1, 2018 at 9:45 AM Alex Bradbury <asb at asbradbury.org> wrote: > >> On Thu, 11 Oct 2018 at 00:28, Thomas Lively via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >> > >&...
2018 Nov 01
2
Proposed new min and max intrinsics
On Thu, 11 Oct 2018 at 00:28, Thomas Lively via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I just wanted to bump this to see if anyone has any input. I would really like to get these landed soon if there are no objections. Hi Thomas, With ISD::FMINNAN and ISD::FMAXNAN now easy to produce for any target due to these newly exposed intrinsics, I think these nodes should be handled
2020 Nov 17
1
RFC: Multiple program address spaces
Fixing llvm-dev at llvm.org to llvm-dev at lists.llvm.org On Tue, Nov 17, 2020 at 11:27 AM Thomas Lively <tlively at google.com> wrote: > Thanks for your work on this, Paulo! > > Here's some more detail about how function pointers work today in the > WebAssembly backend and how they differ from the `funcref` Paulo is > working on. > > Today in the WebAssembly backend, both function...
2019 Nov 19
2
Question about physical registers in ISel
Hi Quentin, Thanks, that explanation makes sense. I can see that in a normal register machine, implicitly defs must be physical registers. In a stack machine like WebAssembly, though, implicit defs are known to be pushed onto the value stack just like any other defs. Slots on the value stack are represented by virtual registers until stackification, so for WebAssembly we do need the implicit defs
2020 Jun 30
3
LLVM Incubator + new projects draft
> On Jun 30, 2020, at 11:52 AM, Roman Lebedev <lebedev.ri at gmail.com> wrote: > > On Tue, Jun 30, 2020 at 9:44 PM Chris Lattner via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> The idea of adding an “incubation” stage to projects in the LLVM world seems to be positively received. I also noticed that we don’t really document the new project policy in
2004 Nov 20
0
ffmpeg2theora start and end time support
For last few days I was trying to learn ffmpeg and libtheora API. In the process, I have modified ffmpeg2theora code to include support for start time and end time. ffmpeg2theora -s 60 -e 130 file.avi will produce file.ogg which will be from 60th to 130th second of input file (something like -ss and -endpos in mencoder). This is a useful feature for someone who wants to cut a part of video
2018 Nov 05
5
Safe fptoui/fptosi casts
I would be interested in learning what the set of used semantics for float-to-int conversion is. If the only two used are 1) undefined behavior if unrepresentable and 2) saturate to int_{min,max} with NaN going to zero, then I think it makes sense to expose both of those natively in the IR. If the set is much larger, I think separate intrinsics for each behavior would make sense. It would be nice
2020 Aug 05
2
Debugging a potential bug when generating wasm32
Hi, Sorry if you've seen this message before on llvm.discourse.group or elsewhere -- I've been trying to get to the bottom of this for a while now and asked about this in a few different platforms before. I'm currently trying to debug a bug in a LLVM-generated Wasm code. The bug could be in the code that generates LLVM (rustc) or in the LLVM, I'm not sure yet. LLVM IR and Wasm
2018 Nov 09
3
Proposed new min and max intrinsics
On Thu, Nov 8, 2018 at 11:35 PM Fabian Giesen via llvm-dev < llvm-dev at lists.llvm.org> wrote: > What is so complicated about these? Shouldn't they just correspond to > two compares + selects? > > To give a concrete example, x86 MIN[SP][SD] and MAX[SP][SD], > respectively, correspond exactly to > > MIN*: select(a < b, a, b) (i.e. "a < b ? a : b")
2020 Aug 31
3
Inlining with different target features
David, That's right, WebAssembly does not have a way to conditionally use a feature or even do runtime feature testing right now. It's on our roadmap of things to design and standardize, but it is still a long way off. > Another direction would be to require the features to be specified consistently for all components of the build, I guess - if that's the net effect anyway. Would