search for: tldrpci

...s Constant Pool: cp#0: @foo, align=4 Function Live Ins: $r0 in %0, $r1 in %1, $r2 in %2 0B bb.0.entry: liveins: $r0, $r1, $r2 16B %2:tgpr = COPY $r2 32B %1:tgpr = COPY $r1 48B %0:tgpr = COPY $r0 64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s...

..., at location [SP-8] Constant Pool: cp#0: -2048, align=4 cp#1: 2048, align=4 BB#0: derived from LLVM BB %entry Live Ins: %R4 %LR tPUSH pred:14, pred:%noreg, %R4<kill>, %LR<kill>, %SP<imp-def>, %SP<imp-use>; flags: FrameSetup %vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags: FrameSetup tGPR:%vreg0 %SP<def,tied1> = tADDhirr %SP<tied0>, %vreg0<kill>, pred:14, pred:%noreg; tGPR:%vreg0 %vreg1<def> = tLDRpci <cp#1>, pred:14, pred:%noreg; tGPR:%vreg1 %SP<def,tied1> = t...

...stant Pool: > cp#0: -2048, align=4 > cp#1: 2048, align=4 > > BB#0: derived from LLVM BB %entry > Live Ins: %R4 %LR > tPUSH pred:14, pred:%noreg, %R4<kill>, %LR<kill>, %SP<imp-def>, %SP<imp-use>; flags: FrameSetup > %vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags: FrameSetup tGPR:%vreg0 > %SP<def,tied1> = tADDhirr %SP<tied0>, %vreg0<kill>, pred:14, pred:%noreg; tGPR:%vreg0 > %vreg1<def> = tLDRpci <cp#1>, pred:14, pred:%noreg; tGPR:%vreg1 > %SP<def,tied1&...

...lign=4 >> cp#1: 2048, align=4 >> >> BB#0: derived from LLVM BB %entry >> Live Ins: %R4 %LR >> tPUSH pred:14, pred:%noreg, %R4<kill>, %LR<kill>, %SP<imp-def>, >> %SP<imp-use>; flags: FrameSetup >> %vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags: >> FrameSetup tGPR:%vreg0 >> %SP<def,tied1> = tADDhirr %SP<tied0>, %vreg0<kill>, pred:14, >> pred:%noreg; tGPR:%vreg0 >> %vreg1<def> = tLDRpci <cp#1>, pred:14, pred:%noreg; tGPR:%vreg1 &gt...

...implicit killed $r0, implicit killed $r1, implicit killed $r2 folded: 144r tBL 14, $noreg, &"\E0\9C\06\A0\FC\7F", implicit-def $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2 :: (load 4 from constant-pool) remat: 228r %10:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 232e %7:tgpr = COPY killed %10:tgpr Could you please point out what am I doing wrong in the patch ? Also, I guess, it only converted two calls to bl because further spilling wasn't necessary. However for above case, IIUC,...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

Hi, While working on https://reviews.llvm.org/D79785, we wanted to define foldMemoryOperandImpl hook for Thumb1, that folds load, indirect call to direct call tLDRpci, tBLX -> tBL. This triggered an assertion error with expensive checks turned on in MachineVerifier because the newly created tBL insn by Thumb1InstrInfo::foldMemoryOperandImpl had memory operands of LoadMI attached by TargetInstrInfo::foldMemoryOperand, which is done unconditionally: // Copy th...

CallFrameSetupOpcode is a pseudo opcode like X86::ADJCALLSTACKDOWN64. That means when the code is expected to be called before the pseudo instructions are eliminated. I don't know why it's not the case for you. A quick look at PEI code indicates the pseudo's should not have been removed at the time when replaceFrameIndices are run. Evan On Sep 25, 2013, at 8:57 AM, Krzysztof

...n > > On Sep 7, 2020, at 2:17 AM, Prathamesh Kulkarni via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > While working on https://reviews.llvm.org/D79785, we wanted to define > foldMemoryOperandImpl hook for Thumb1, that folds load, indirect call > to direct call tLDRpci, tBLX -> tBL. This triggered an assertion > error with expensive checks turned on in MachineVerifier because the > newly created tBL insn by > Thumb1InstrInfo::foldMemoryOperandImpl had memory operands of LoadMI > attached by TargetInstrInfo::foldMemoryOperand, which is done > unc...

Hi All, I'm dealing with a problem where the spill/restore instructions inserted during scavenging span an adjustment of the SP/FP register. The result is that despite the base register (SP/FP) being changed between the spill and the restore, both store and load use the same immediate offset. I see code in the PEI (replaceFrameIndices) that is supposed to track the SP/FP adjustment:

..., implicit killed $r1, implicit killed $r2 > folded: 144r tBL 14, $noreg, &"\E0\9C\06\A0\FC\7F", > implicit-def $lr, implicit $sp, implicit killed $r0, implicit killed > $r1, implicit killed $r2 :: (load 4 from constant-pool) > remat: 228r %10:tgpr = tLDRpci %const.0, 14, $noreg :: > (load 4 from constant-pool) > 232e %7:tgpr = COPY killed %10:tgpr > > Could you please point out what am I doing wrong in the patch ? > > Also, I guess, it only converted two calls to bl because further > spilling wasn't necessar...