Displaying 5 results from an estimated 5 matches for "tjkenney".
Did you mean:
mckenney
2016 Aug 23
2
Help in understanding physreg LiveVariables
...rom: Matthias Braun <mbraun at apple.com>
To: Tyler Kenney/Marlborough/IBM at IBMUS
Cc: llvm-dev at lists.llvm.org
Date: 08/23/2016 05:17 PM
Subject: Re: [llvm-dev] Help in understanding physreg LiveVariables
Sent by: mbraun at apple.com
On Aug 23, 2016, at 2:07 PM, Tyler Kenney <tjkenney at us.ibm.com>
wrote:
So if I create a value with a DAG.getUndef(myVT); call during
instruction legalization, how can I access that value as input in
another BB/DAG (also during instruction legalization) without
worrying about live-ins and/or phi nodes?
Ca...
2016 Aug 23
2
Help in understanding physreg LiveVariables
...rom: Matthias Braun <mbraun at apple.com>
To: Tyler Kenney/Marlborough/IBM at IBMUS
Cc: llvm-dev at lists.llvm.org
Date: 08/23/2016 04:43 PM
Subject: Re: [llvm-dev] Help in understanding physreg LiveVariables
Sent by: mbraun at apple.com
On Aug 23, 2016, at 1:38 PM, Tyler Kenney <tjkenney at us.ibm.com>
wrote:
Matthias,
Thanks for the response.
In short, I'm using physregs because my current design, in some
cases, needs to create an entirely new var/reg during instruction
legalization. This value can be passed from one basic block to...
2015 Jul 30
2
[LLVMdev] Question on BlendSplat Code - LLVM Commit 72753f87f2b80d66cfd7ca7c7b6c0db6737d4b24
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150730/121669c8/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: blend-splat-test.tar.gz
Type: application/octet-stream
Size: 11716 bytes
Desc: not available
URL:
2016 Aug 23
2
Help in understanding physreg LiveVariables
<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" >Matthias,</div>
<div dir="ltr" > </div>
<div dir="ltr" >Thanks for the response.</div>
<div
2016 Jun 01
4
Adding BB input/output registers during ISel
Hello all,
I am developing an out-of-tree backend for a unique simd processor and I'm
looking for a bit of help. In my current design, it's possible for a case
to arise where I decide during instruction legalization that a fixed-sized
array of vectors which has been initially allocated on the stack needs to
be lowered into the vector register file. I have this design working for
the case