Displaying 8 results from an estimated 8 matches for "timing_10_cl".
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timing_10_cwl
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2014 Sep 29
0
[PATCH 1/7] fb/gddr3: Generate MR values
...docs */
+ { 4, 1 }, { 6, 3 }, { 12, 1 }, { 13 , 2 },
+ { -1 }
+};
+
+int
+nouveau_gddr3_calc(struct nouveau_ram *ram)
+{
+ int CL, WR, CWL, DLL = 0, ODT = 0, hi;
+
+ switch (ram->next->bios.timing_ver) {
+ case 0x10:
+ CWL = ram->next->bios.timing_10_CWL;
+ CL = ram->next->bios.timing_10_CL;
+ WR = ram->next->bios.timing_10_WR;
+ DLL = !ram->next->bios.ramcfg_10_DLLoff;
+ ODT = ram->next->bios.timing_10_ODT;
+ break;
+ case 0x20:
+ CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
+ CL = (ram->next->bios.timing[1] & 0x0000001f) &g...
2015 Jul 05
1
[RFC] Fermi/Kepler identify DLLoff
Hello,
Attached a small patch that correctly identifies the DLLoff bit for >=GF100.
Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd
like to verify whether the DLL should be reset when enabled. Could increase
likelihood of succesfull reclock.
Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL
reset logic?
Thanks, and happy
2017 Apr 10
0
[PATCH 03/11] nvkm/gddr5: MR calculation for timing table v1.0
...>bios.ramcfg_11_06;
l3 = !ram->next->bios.ramcfg_11_07_02;
break;
default:
@@ -54,6 +58,15 @@ nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts)
}
switch (ram->next->bios.timing_ver) {
+ case 0x10:
+ WL = ram->next->bios.timing_10_CWL;
+ CL = ram->next->bios.timing_10_CL;
+ WR = ram->next->bios.timing_10_WR;
+ at[0] = ram->next->bios.timing_10_ADRCMD_T & 0x3;
+ at[1] = 0;
+ dt = ram->next->bios.timing_10_ODT;
+ ds = ram->next->bios.timing_10_DS;
+ break;
case 0x20:
WL = (ram->next->bios.timing[1] & 0x00000f80) >&g...
2015 May 22
11
Reclocking support for NVA0
Adds reclocking for NVA0, and a whole lot of work for other cards. Had these
patches collecting dust for a little, but tested them with both my NVA0,
and Martin's a while back. Success not guaranteed, but should be quite a
leap forward.
Happy reviewing and testing. Cheers,
Roy
2015 Sep 29
10
All-round reclocking improvements
In bulletpoints:
- Add some support for G94 and G96 reclocking. Has been tested on literally
two cards, which is hardly adequate as "full coverage". On the other hand,
the changes were small enough to make me confident this might work for others
as well.
- Fix NV50 wait for VBLANK when no monitor is plugged in.
- Voltage related inprovements for GT21x.
- Slightly improve Keplers
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern