Displaying 7 results from an estimated 7 matches for "timing_10_21".
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timing_10_24
2017 Nov 02
0
[PATCH] drm/nouveau/bios/timing: mark expected switch fall-throughs
...+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
@@ -115,16 +115,21 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
switch (min_t(u8, *hdr, 25)) {
case 25:
p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
+ /* fall through */
case 24:
case 23:
case 22:
p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
+ /* fall through */
case 21:
p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
+ /* fall through */
case 20:
p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
+ /* fall through */
case 19:
p->timing_10_18 = nvbios_rd08(bios,...
2020 Jul 07
3
[PATCH][next] drm/nouveau: Use fallthrough pseudo-keyword
.../drm/nouveau/nvkm/subdev/bios/timing.c
@@ -115,21 +115,21 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
switch (min_t(u8, *hdr, 25)) {
case 25:
p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
- /* fall through */
+ fallthrough;
case 24:
case 23:
case 22:
p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
- /* fall through */
+ fallthrough;
case 21:
p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
- /* fall through */
+ fallthrough;
case 20:
p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
- /* fall through */
+ fallthrough;
c...
2015 May 24
3
[PATCH v2 07/10] bios/ramcfg: Separate out RON pull value
...10_RRD = nv_ro08(bios, data + 0x0c);
p->timing_10_13 = nv_ro08(bios, data + 0x0d);
p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
+ if (p->ramcfg_ver >= 0x10)
+ p->ramcfg_RON = nv_ro08(bios, data + 0x0e) & 0x07;
p->timing_10_24 = 0xff;
p->timing_10_21 = 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
index e1d11f7..8d759f8a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
@@ -70,7 +70,7 @@ ramgddr3_wr_lo[] = {
int
nv...
2020 Jul 08
0
[PATCH][next] drm/nouveau: Use fallthrough pseudo-keyword
...:
> p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
> - /* fall through */
> + fallthrough;
> case 24:
> case 23:
> case 22:
> p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
> - /* fall through */
> + fallthrough;
> case 21:
> p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
> - /* fall through */
> +...
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2015 May 22
11
Reclocking support for NVA0
Adds reclocking for NVA0, and a whole lot of work for other cards. Had these
patches collecting dust for a little, but tested them with both my NVA0,
and Martin's a while back. Success not guaranteed, but should be quite a
leap forward.
Happy reviewing and testing. Cheers,
Roy