search for: timer_deadline

Displaying 4 results from an estimated 4 matches for "timer_deadline".

2009 Apr 30
0
[PATCH] cpuidle: Fix for timer_deadline==0 case
cpuidle: Fix for timer_deadline==0 case After the scheduler timer became suspended before entering cpu idle state, the percpu timer_deadline is possible to be 0, i.e. no soft timer in the queue. This case will cause unexpected large residency percentage in C1 for the purely idle cpu. The fix is if timer_deadline == 0, skip most...
2008 Jul 16
1
[PATCH] Adjust handle_hpet_broadcast to let it run better before broadcast exit
...spin_lock(&ch->lock); - if ( cpu_isset(current_cpu, ch->cpumask) ) - printk(KERN_DEBUG "WARNING: current cpu%d in bc_mask\n", current_cpu); again: ch->next_event = STIME_MAX; next_event = STIME_MAX; @@ -162,8 +158,6 @@ again: else if ( per_cpu(timer_deadline, cpu) < next_event ) next_event = per_cpu(timer_deadline, cpu); } - if ( per_cpu(timer_deadline, current_cpu) <= now ) - cpu_set(current_cpu, mask); /* wakeup the cpus which have an expired event. */ evt_do_broadcast(mask); ____________________________...
2011 Mar 28
0
[xen-unstable test] 6714: regressions - FAIL
...23096:a65612bcbb92 user: Jan Beulich <jbeulich@novell.com> date: Fri Mar 25 09:03:17 2011 +0000 x86/hpet: eliminate cpumask_lock According to the (now getting removed) comment in struct hpet_event_channel, this was to prevent accessing a CPU''s timer_deadline after it got cleared from cpumask. This can be done without a lock altogether - hpet_broadcast_exit() can simply clear the bit, and handle_hpet_broadcast() can read timer_deadline before looking at the mask a second time (the cpumask bit was already found set by the surrounding loop...
2012 Feb 08
18
[PATCH 0 of 4] Prune outdated/impossible preprocessor symbols, and update VIOAPIC emulation
Patch 1 removes CONFIG_SMP Patch 2 removes separate smp_{,r,w}mb()s as a result of patch 1 Patch 4 removes __ia64__ defines from the x86 arch tree Patch 3 is related to patch 4 and changes the VIOAPIC to emulate version 0x20 as a performance gain. It preceeds Patch 4 so as to be more clear about the functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>