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...ngjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/14/20 6:27 AM, Luo, Yuanke via llvm-dev wrote: Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability of Intel AMX implementation is enumerated by palettes. Two palettes are supported: palette 0 represents the initialized state and palette 1 consists of 8 tile registers of up to...

...ues and the hardware details to prevent this. We'll also want a diagnostic that lets the user know when this has happened. When the tile configuration is set, the shape of each tile is locked in, so the individual tile registers aren't interchangeable at that point. If a function needs 2x4 tiles, 4x2 tiles, and 4x4 tiles, the configuration needs to be set with this in mind. The shape isn't explicit in every instruction and intrinsic. It must be deduced. And again, we'll need a way to tell the user when efficient allocation can't be done. In practice, I don't expect any func...

...craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. Hi, Andy, I don't quite understand everything that's going on here. Could we model this as: 1. Define a collection of register classes, one for 2x4 tiles, one for 4x2 tiles, etc. each populated with a set of tile registers. Registers can have aliasing relationships (instead of worrying of any kind of subregister/superregister relationships -- these won't be useful anyway). 2. Define the tile-configuration instructions so that they implicitly d...

...onfigure the tile register. I think your suggestion is helpful to reduce the complexity if we only support fixed (constant) tile shape. -Yuanke Thanks, Yuanke. It's not clear to me that having 256 register classes is, in itself, a problem. Is it? What does it mean to support variable-shape tiles in this context? Do you do something other than conservatively assume that they are 16x16 for register-allocation purposes? -Hal From: Hal Finkel <hfinkel at anl.gov><mailto:hfinkel at anl.gov> Sent: Wednesday, August 19, 2020 8:20 AM To: Kaylor, Andrew <andrew.kaylor at intel.c...

The width and height can be runtime values that we would just copy into 64 byte configuration block we pass to ldtilecfg. So the code doesn't need to be multiversioned. The user code would also use those values to update pointers in the loops they write using the tiles. If we can't determine that two tiles were defined with the same width and height we need to assume the shape is different and try to avoid ever giving the same tile. Hal, for your suggestion would which physical registers are in which register class be defined dynamically before register alloc...

> When the tile shape is unknown at compile time, how do you plan to do the register allocation of the tiles? My question is: do you do the allocation for this case in the same way as you would if you knew the size was 16x16 (i.e., conservatively assume the largest size)? I think what will happen is that the registers are allocated based on a number of runtime values that are assumed to be different from...

Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability of Intel AMX implementation is enumerated by palettes. Two palettes are supported: palette 0 represents the initialized state and palette 1 consists of 8 tile registers of up to...

...is per > tile. The multiply instructions take a MxK tile and multiply it by a > KxN tile and accumulate into an MxN tile. So the configuration needs > to know how many of each size of tile it needs to avoid a spill. > Wouldn’t the register allocator then need to know which physical tiles > have been configured to which sizes so that it only chooses those > tiles for an operand that needs that size? > Yes, I think so. But it will because that information is essentially encoded in the virtual register classes. I certainly could be missing something. It seems like you fi...

...0 3:09 PM, Topper, Craig wrote: The width and height can be runtime values that we would just copy into 64 byte configuration block we pass to ldtilecfg. So the code doesn't need to be multiversioned. The user code would also use those values to update pointers in the loops they write using the tiles. If we can't determine that two tiles were defined with the same width and height we need to assume the shape is different and try to avoid ever giving the same tile. Hal, for your suggestion would which physical registers are in which register class be defined dynamically before register alloc...

...lt;mailto:hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/14/20 6:27 AM, Luo, Yuanke via llvm-dev wrote: Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability of Intel AMX implementation is enumerated by palettes. Two palettes are supported: palette 0 represents the initialized state and palette 1 consists of 8 tile registers of up to...

...ngjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/14/20 8:27 AM, Luo, Yuanke via llvm-dev wrote: Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability of Intel AMX implementation is enumerated by palettes. Two palettes are supported: palette 0 represents the initialized state and palette 1 consists of 8 tile registers of up to...

...tile/hvconfig > >> Detailed configuration description of the hypervisor config > > I'm concerned about moving this one out of /proc, since it's just (copious) > free text. An "hvconfig" (hypervisor config) file describes hypervisor > driver "dedicated tiles" that run things like network packet or PCIe > ingress/egress processing, etc. In addition it lists hypervisor driver > options, boot flags for the kernel, etc, all kinds of things -- and you > can't really guarantee that it will fit on a 4KB page, though in practice > it usua...

...tile/hvconfig > >> Detailed configuration description of the hypervisor config > > I'm concerned about moving this one out of /proc, since it's just (copious) > free text. An "hvconfig" (hypervisor config) file describes hypervisor > driver "dedicated tiles" that run things like network packet or PCIe > ingress/egress processing, etc. In addition it lists hypervisor driver > options, boot flags for the kernel, etc, all kinds of things -- and you > can't really guarantee that it will fit on a 4KB page, though in practice > it usua...

...buys us anything, so please disregard that suggestion of mine. Use only one register class. Once the configuration regions are identified, you'll know how many tile register shapes are required. If this number is greater than eight, then you'll need to cut the region (requiring all live tiles to be spilled and restored around each re-configuration point). After that, we'll assume that we have eight or fewer distinct shapes. Now the problem is that you need to allocate registers, satisfying all of the usual constraints (non-overlapping live ranges, etc.), but with an additional...

...t; please disregard that suggestion of mine. Use only one register class. > > Once the configuration regions are identified, you'll know how many > tile register shapes are required. If this number is greater than > eight, then you'll need to cut the region (requiring all live tiles to > be spilled and restored around each re-configuration point). After > that, we'll assume that we have eight or fewer distinct shapes. > > Now the problem is that you need to allocate registers, satisfying all > of the usual constraints (non-overlapping live ranges, etc.),...

...ly buys us anything, so please disregard that suggestion of mine. Use only one register class. Once the configuration regions are identified, you'll know how many tile register shapes are required. If this number is greater than eight, then you'll need to cut the region (requiring all live tiles to be spilled and restored around each re-configuration point). After that, we'll assume that we have eight or fewer distinct shapes. Now the problem is that you need to allocate registers, satisfying all of the usual constraints (non-overlapping live ranges, etc.), but with an additional cons...

In the help for scale_fill_identity, it is written ## Not run: colour <- c("red","green","blue","yellow") qplot(1:4, 1:4, fill=colour, geom="tile") qplot(1:4, 1:4, fill=colour, geom="tile") + scale_fill_identity() # To get a legend, you also need to supply the labels to # be used

Please ignore the tegra diff on the bottom of this. I never fail to find a way to mess up git-send-email. -James On 12/11/19 12:59 PM, James Jones wrote: > This series modifies the NV5x+ nouveau display backends to advertise > appropriate format modifiers on their display planes in atomic mode > setting blobs. > > Corresponding modifications to Mesa/userspace are available

...|") voro = deldir(points$x,points$y,digits=10,frac=0.000000000000001,rw=c(min(points$x)-abs(min(points$x)-max(points$x)),max(points$x)+abs(min(points$x)-max(points$x)),min(points$y)-abs(min(points$y)-max(points$y)),max(points$y)+abs(min(points$y)-max(points$y)))) # generate voronoi edges tiles = tile.list(voro) # combine edges into polygons sink("voronoi.sql") # redirect output to file for (i in 1:length(tiles)) { # write out polygons tile = tiles[[i]] cat("insert into mytable (the_geom) values(geomfromtext('POLYGON((")...

I just checkout release_38 branches of llvm, clang and polly and built it on and x86 Ubuntu with cmake: CMAKE_BUILD_TYPE="Debug" CMAKE_INSTALL_PREFIX="$HOME/toolchain/install/llvm-3.8" LLVM_TARGETS_TO_BUILD="X86" cmake -G "Unix Makefiles" \ -DBUILD_SHARED_LIBS="ON" \ -DCMAKE_BUILD_TYPE=$CMAKE_BUILD_TYPE \