Displaying 5 results from an estimated 5 matches for "thexor".
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...Ciao,
Duncan.
>> then there is another optimization afterwards..
>>
>> // Transform br(xor(x, y)) -> br(x != y)
>> // Transform br(xor(xor(x,y), 1)) -> br (x == y)
>> if (N1.hasOneUse()&& N1.getOpcode() == ISD::XOR) {
>> SDNode *TheXor = N1.getNode();
>> SDValue Op0 = TheXor->getOperand(0);
>> SDValue Op1 = TheXor->getOperand(1);
>> if (Op0.getOpcode() == Op1.getOpcode()) {
>> // Avoid missing important xor optimizations.
>> SDValue Tmp = visitXOR(TheXor);
>>...
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...;
N1 = N1.getOperand(0);
}
which just drops the truncate away..
then there is another optimization afterwards..
// Transform br(xor(x, y)) -> br(x != y)
// Transform br(xor(xor(x,y), 1)) -> br (x == y)
if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
SDNode *TheXor = N1.getNode();
SDValue Op0 = TheXor->getOperand(0);
SDValue Op1 = TheXor->getOperand(1);
if (Op0.getOpcode() == Op1.getOpcode()) {
// Avoid missing important xor optimizations.
SDValue Tmp = visitXOR(TheXor);
if (Tmp.getNode() && Tmp.getNode() != T...
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...gt;
> which just drops the truncate away..
> then there is another optimization afterwards..
>
> // Transform br(xor(x, y)) -> br(x != y)
> // Transform br(xor(xor(x,y), 1)) -> br (x == y)
> if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
> SDNode *TheXor = N1.getNode();
> SDValue Op0 = TheXor->getOperand(0);
> SDValue Op1 = TheXor->getOperand(1);
> if (Op0.getOpcode() == Op1.getOpcode()) {
> // Avoid missing important xor optimizations.
> SDValue Tmp = visitXOR(TheXor);
> if (Tmp.getNode() &...
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>
>> Our architecture has 1-bit boolean predicate registers.
>>
>> I've defined comparison
>>
>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
> Our architecture has 1-bit boolean predicate registers.
>
> I've defined comparison
>
>
> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>
>
>
>
> But then I end up having the following bug:
>
>