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...m llvm/utils/TableGen/AsmMatcherEmitter.cpp (so it needs to be commented to be disabled): // The first token of the instruction is the mnemonic, which must be a // simple string, not a $foo variable or a singleton register. if (AsmOperands.empty()) PrintFatalError(TheDef->getLoc(), "Instruction '" + TheDef->getName() + "' has no tokens"); assert(!AsmOperands[0].Token.empty()); if (HasMnemonicFirst) { Mnemonic = AsmOperands[0].Token; if (Mnemonic[0] == '$')...

Hello, InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: if (!Hack) PrintFatalError(TheDef->getLoc(), "ERROR: matchable with tied operand '" + Tok + "' can never be matched!"); // FIXME: Should reject these. The ARM backend hits this with $lane in a // bunch of instructions. It is unclear wh...

...lt;llvm-dev at lists.llvm.org> wrote: > > Hello, > > InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. > > It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: > > if (!Hack) > PrintFatalError(TheDef->getLoc(), > "ERROR: matchable with tied operand '" + Tok + > "' can never be matched!"); > // FIXME: Should reject these. The ARM backend hits this with $lane in a > // bunch of instructions. It is...

Could we expose predicates defined in the target InstrInfo.td file to the MachineVerifier? We use BuildMI() to create many instructions after ISEL, but the predicates are not being checked at this point. Thus, I could forget to check the target and build an instruction that is illegal for a specific configuration. In such a case it would be nice if the MachineVerifier could detect this for me.

...follows: I have defined a set of registers with rather similar names including digits. The code section at RegisterInfoEmitter::run(){ ... // Process sub-register sets. runs and fills the RegisterAliases map. then, ... for (unsigned i = 0, e = Regs.size(); i != e; ++i) { RegNo[Regs[i].TheDef] = i; NumAliases += RegisterAliases[Regs[i].TheDef].size(); } runs. Only, now there are duplicates in the RegisterAliases map for the same Regs[i]-Record. This lead to duplicate output of the REG_Overlaps lists: error: redefinition of 'const unsigned int llvm::<unnamed>::a23g_Overl...

I have a question about the code in utils/TableGen/FixedLenDecoderEmitter.cpp (line 1150). bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, unsigned Opc) const { ListInit *Predicates = AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates"); for (unsigned i = 0; i < Predicates->getSize(); ++i) { Record *Pred = Predicates->getElementAsRecord(i); if (!Pred->getValue("AssemblerMatcherPredicate")) continue; The code above seems to be checking whether the...

...gt; Hello, >> >> InstAlias does not allow tied operands (repeated operands) in the asm >> string to be matched. >> >> It seems this situation is explicitly prevented in >> AsmMatcherEmitter.cpp: >> >> if (!Hack) >> PrintFatalError(TheDef->getLoc(), >> "ERROR: matchable with tied operand '" + Tok + >> "' can never be matched!"); >> // FIXME: Should reject these. The ARM backend hits this with >> $lane in a >> // bun...

Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST:

...eSeq.back(); WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name); - // If this Write is not referenced by a ReadAdvance, don't distinguish it - // from other WriteLatency entries. - if (!SchedModels.hasReadOfWrite( - SchedModels.getSchedWrite(WriteID).TheDef)) { - WriteID = 0; - } + WLEntry.WriteResourceID = WriteID;