Displaying 4 results from an estimated 4 matches for "tgsi_writemask_x".
2009 Dec 31
1
[PATCH] Autogenerate uureg opcode macros
..., Z, Y, Z, Y)
#define _zw(v) _swz(v, Z, W, Z, W)
+#define _ind(r, a) ureg_src_indirect(_src(r), _src(a))
+#define _abs(x) ureg_abs(_src(x))
+#define _neg(x) ureg_negate(_src(x))
+#define _undef ureg_src_undef()
+#define _is_undef(v) ureg_src_is_undef(_src(v))
+
+#define _X(v) ureg_writemask((v), TGSI_WRITEMASK_X)
+#define _Y(v) ureg_writemask((v), TGSI_WRITEMASK_Y)
+#define _Z(v) ureg_writemask((v), TGSI_WRITEMASK_Z)
+#define _W(v) ureg_writemask((v), TGSI_WRITEMASK_W)
+#define _XY(v) ureg_writemask((v), TGSI_WRITEMASK_X | TGSI_WRITEMASK_Y)
+#define _XZ(v) ureg_writemask((v), TGSI_WRITEMASK_X | TGSI_WRITEM...
2017 Jun 11
0
[RFC 4/9] tgsi: populate precise
...nine_shader.c b/src/gallium/state_trackers/nine/nine_shader.c
index 40fb6be88f..f405090811 100644
--- a/src/gallium/state_trackers/nine/nine_shader.c
+++ b/src/gallium/state_trackers/nine/nine_shader.c
@@ -1879,7 +1879,7 @@ DECL_SPECIAL(IFC)
struct ureg_dst tmp = ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_X);
src[0] = tx_src_param(tx, &tx->insn.src[0]);
src[1] = tx_src_param(tx, &tx->insn.src[1]);
- ureg_insn(tx->ureg, cmp_op, &tmp, 1, src, 2);
+ ureg_insn(tx->ureg, cmp_op, &tmp, 1, src, 2, 0);
ureg_IF(tx->ureg, ureg_scalar(ureg_src(tmp), TGSI_SWIZZL...
2017 Jun 11
14
[RFC 0/9] Add precise/invariant semantics to TGSI
Running Tomb Raider on Nouveau I found some flicker caused by ignoring precise
modifiers on variables inside Nouveau.
This series add precise/invariant handling to TGSI, which can be then used by
drivers to disable certain unsafe optimisations which may otherwise alter
calculations, which depend on having the same result across shaders.
This series fixes this bug in Tomb Raider and one CTS test
2010 Aug 06
4
nv vpe video decoder
Hello,
I have my work on the nv vpe video decoder in a functional
state. In case you didn't know this decoder accelerates mpeg2
video at the idct/mc level. I have verified that it works on
nv40 hardware. I believe it works on nv30 hardware (and
maybe some earlier hardware), but I cannot verify since I have
none.
I will reply with patches against the kernel, drm, ddx
and mesa for