Displaying 3 results from an estimated 3 matches for "tgsi_opcode_sgt".
2009 Sep 10
0
[PATCH 06/13] nv50: handle SEQ, SGT, SLE, SNE opcodes
..., dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
+ if (rdst && rdst != dst)
free_temp(pc, dst);
}
+static INLINE unsigned
+map_tgsi_setop_cc(unsigned op)
+{
+ switch (op) {
+ case TGSI_OPCODE_SLT: return 0x1;
+ case TGSI_OPCODE_SGE: return 0x6;
+ case TGSI_OPCODE_SEQ: return 0x2;
+ case TGSI_OPCODE_SGT: return 0x4;
+ case TGSI_OPCODE_SLE: return 0x3;
+ case TGSI_OPCODE_SNE: return 0xd;
+ default:
+ assert(0);
+ return 0;
+ }
+}
+
static INLINE void
emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
{
@@ -1606,13 +1638,6 @@ nv50_program_tx_insn(struct nv50_pc *pc,
if...
2009 Jun 21
0
[PATCH] nv50: support for SLE, SNE, SEQ, SGT
...t_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
emit(pc, e);
}
+static inline unsigned
+map_opcode_ccode(unsigned op)
+{
+ switch (op) {
+ case TGSI_OPCODE_SLT: return TGSI_CC_LT;
+ case TGSI_OPCODE_SGE: return TGSI_CC_GE;
+ case TGSI_OPCODE_SEQ: return TGSI_CC_EQ;
+ case TGSI_OPCODE_SGT: return TGSI_CC_GT;
+ case TGSI_OPCODE_SLE: return TGSI_CC_LE;
+ case TGSI_OPCODE_SNE: return TGSI_CC_NE;
+ default:
+ assert(0);
+ return 0;
+ }
+}
+
+static inline unsigned
+map_ccode_nv50(unsigned cc)
+{
+ assert(cc < 16);
+
+ switch (cc) {
+ case TGSI_CC_GT: return 0x4;
+ case TGSI_CC_EQ:...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---