Displaying 10 results from an estimated 10 matches for "tgsi_opcode_pow".
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tgsi_opcode_mov
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...0_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -2199,7 +2199,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> case TGSI_OPCODE_IMUL_HI:
> case TGSI_OPCODE_UMUL_HI:
> case TGSI_OPCODE_OR:
> - case TGSI_OPCODE_POW:
> case TGSI_OPCODE_SHL:
> case TGSI_OPCODE_ISHR:
> case TGSI_OPCODE_USHR:
> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> mkOp1(OP_MOV, TYPE_U32, dst0[c], fet...
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...m/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>>> @@ -2199,7 +2199,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> case TGSI_OPCODE_IMUL_HI:
>>> case TGSI_OPCODE_UMUL_HI:
>>> case TGSI_OPCODE_OR:
>>> - case TGSI_OPCODE_POW:
>>> case TGSI_OPCODE_SHL:
>>> case TGSI_OPCODE_ISHR:
>>> case TGSI_OPCODE_USHR:
>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>...
2014 May 20
0
[PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...um/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2199,7 +2199,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
case TGSI_OPCODE_IMUL_HI:
case TGSI_OPCODE_UMUL_HI:
case TGSI_OPCODE_OR:
- case TGSI_OPCODE_POW:
case TGSI_OPCODE_SHL:
case TGSI_OPCODE_ISHR:
case TGSI_OPCODE_USHR:
@@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
break;
+...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...gt; +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> @@ -2199,7 +2199,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> case TGSI_OPCODE_IMUL_HI:
>> case TGSI_OPCODE_UMUL_HI:
>> case TGSI_OPCODE_OR:
>> - case TGSI_OPCODE_POW:
>> case TGSI_OPCODE_SHL:
>> case TGSI_OPCODE_ISHR:
>> case TGSI_OPCODE_USHR:
>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>> mkOp1(OP_MOV...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...degen/nv50_ir_from_tgsi.cpp
>>>> @@ -2199,7 +2199,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> case TGSI_OPCODE_IMUL_HI:
>>>> case TGSI_OPCODE_UMUL_HI:
>>>> case TGSI_OPCODE_OR:
>>>> - case TGSI_OPCODE_POW:
>>>> case TGSI_OPCODE_SHL:
>>>> case TGSI_OPCODE_ISHR:
>>>> case TGSI_OPCODE_USHR:
>>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> FOR_EACH_DST_ENABLED_CHANNEL(0,...
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
...re any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull out bufctx on context destruction
nv50: setup scissors on clear_render_target/depth_stencil
nv50,nvc0: set constbufs dirty on pipe context switch
nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
nv50/ir/opt: fix constant folding with saturate modifier
nv50/ir: fix lowering of predicated instructions (without defs)
nv50/ir/tgsi: optimize KIL
nv50,nvc0: handle guard band defines
nv50,nvc0: allow 15,16,30 bpp display formats
nvc0: use PRIxPTR for sizeof()
n...
2009 Sep 10
0
[PATCH 01/13] nv50: extend insn src mask function
...((mask & 0x7) ? 0x1 : 0x0);
+ case TGSI_OPCODE_DP3:
+ return 0x7;
+ case TGSI_OPCODE_DP4:
+ case TGSI_OPCODE_DPH:
+ case TGSI_OPCODE_KIL: /* WriteMask ignored */
+ return 0xf;
+ case TGSI_OPCODE_DST:
+ return mask & (c ? 0xa : 0x6);
+ case TGSI_OPCODE_EX2:
+ case TGSI_OPCODE_LG2:
+ case TGSI_OPCODE_POW:
+ case TGSI_OPCODE_RCP:
+ case TGSI_OPCODE_RSQ:
+ case TGSI_OPCODE_SCS:
+ return 0x1;
+ case TGSI_OPCODE_LIT:
+ return 0xb;
+ case TGSI_OPCODE_TEX:
+ case TGSI_OPCODE_TXP:
+ {
+ const struct tgsi_instruction_ext_texture *tex;
+
+ assert(insn->Instruction.Extended);
+ tex = &insn->In...
2009 Sep 10
0
[PATCH 02/13] nv50: add functions for swizzle resolution
...- return FALSE;
-
- switch (insn->Instruction.Opcode) {
- case TGSI_OPCODE_COS:
+ switch (op) {
+ case TGSI_OPCODE_DP2:
case TGSI_OPCODE_DP3:
case TGSI_OPCODE_DP4:
case TGSI_OPCODE_DPH:
- case TGSI_OPCODE_KIL:
- case TGSI_OPCODE_LIT:
+ case TGSI_OPCODE_EX2:
+ case TGSI_OPCODE_LG2:
case TGSI_OPCODE_POW:
case TGSI_OPCODE_RCP:
case TGSI_OPCODE_RSQ:
+ /*
+ case TGSI_OPCODE_COS:
+ case TGSI_OPCODE_KIL:
+ case TGSI_OPCODE_LIT:
case TGSI_OPCODE_SCS:
case TGSI_OPCODE_SIN:
+ */
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+/* Returns a bitmask indicating which dst components depend
+ *...
2014 Feb 21
3
[PATCH 1/4] nv30: remove use_nv4x, it is identical to is_nv4x
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Perhaps there was a day when those were different, but that day is not today.
src/gallium/drivers/nouveau/nv30/nv30_context.c | 1 -
src/gallium/drivers/nouveau/nv30/nv30_context.h | 1 -
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 20 ++++++++++----------
src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c | 8 ++++----
4
2009 May 06
2
nv50: shader generation patches
Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is
what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at
least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues
of the floor texture), arbfplight, and I think the gears also didn't appear as they