search for: tfri

...cessors according to CFG: BB#3 BB#2 > %vreg194<def> = ADDr_MPYir_V4 %vreg185, 120, %vreg187<kill>; > IntRegs:%vreg194,%vreg185,%vreg187 > %vreg195<def> = CONST32_set <ga:@raac_sfBandTabShortOffset>; > IntRegs:%vreg195 > .... > %vreg306<def> = TFRI 127; IntRegs:%vreg306 > %vreg307<def> = TFRI 1; IntRegs:%vreg307 > %vreg438<def> = COPY %vreg193; IntRegs:%vreg438,%vreg193 > %vreg362<def> = COPY %vreg193; IntRegs:%vreg362,%vreg193 > Successors according to CFG: BB#5 > > MachineScheduling xxx:BB#4...

...life. Look at vreg304 below: BB#2: derived from LLVM BB %if.end Predecessors according to CFG: BB#1 %vreg61<def> = LDrih_indexed %vreg56, 3134; IntRegs:%vreg61,%vreg56 %vreg62<def> = LDriuh_indexed %vreg56, 680; IntRegs:%vreg62,%vreg56 %R1<def> = TFRI 1431655766 ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>, %R31<imp-use>, %R30<imp-use>, %R29<imp-use> %vreg304:subreg_loreg<def,read-undef> = ADDri_SUBr_V4 %vreg62, 5, %vreg61; DoubleRegs:%vreg304 IntRegs:%vreg62,%vreg61 %vreg519&l...

...ll>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 <<<<&lt...

...t;fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 16777216; > IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 48B %vreg28<def> = COPY %D1<kill>; D...

...g30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg...

On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote: > The code in collectRanges() does: > > // Collect ranges for register units. These live ranges are computed on > // demand, so just skip any that haven't been computed yet. > if (TargetRegisterInfo::isPhysicalRegister(Reg)) { > for (MCRegUnitIterator Units(Reg,

...2B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 16777216; > IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 >...

The code in collectRanges() does: // Collect ranges for register units. These live ranges are computed on // demand, so just skip any that haven't been computed yet. if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))

...g30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg...

...; >> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] >> IntRegs:%vreg31 >> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 >> 28B %vreg106<def> = TFRI 16777216; >> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop >> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 >> 48B %vreg28<def> = COPY %D1<kil...

On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote: > > I've described that issue (see below) when you were out of town... I think > I am getting more context on it. Please take a look... > > So, in short, when the new MI scheduler performs move of an instruction, it > does something like this: > > // Move the instruction to its new

...ixedStack-1](align=8) IntRegs:%vreg30 > >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > >> IntRegs:%vreg31 > >> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > >> 28B %vreg106<def> = TFRI 16777216; > >> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > >> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > >> 48B %vreg28<def> =...

...t;fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 16777216; > IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 48B %vreg28<def> = COPY %D1<kill>; D...

Andy, I've described that issue (see below) when you were out of town... I think I am getting more context on it. Please take a look... So, in short, when the new MI scheduler performs move of an instruction, it does something like this: // Move the instruction to its new location in the instruction stream. MachineInstr *MI = SU->getInstr(); if (IsTopNode) {

...st { >> return false; >> } >> >> +bool HexagonInstrInfo:: >> +isConditionalTransfer (const MachineInstr *MI) const { >> + switch (MI->getOpcode()) { >> + case Hexagon::TFR_cPt: >> + case Hexagon::TFR_cNotPt: >> + case Hexagon::TFRI_cPt: >> + case Hexagon::TFRI_cNotPt: >> + case Hexagon::TFR_cdnPt: >> + case Hexagon::TFR_cdnNotPt: >> + case Hexagon::TFRI_cdnPt: >> + case Hexagon::TFRI_cdnNotPt: >> + return true; >> + >> + default: >> + return fal...