Displaying 5 results from an estimated 5 matches for "tex_cb_index".
2016 Oct 16
0
[PATCH 2/5] nvc0: make use of the new hwdefs for TEX_CB_INDEX
...a17db..0682806 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0x00000001);
BEGIN_NVC0(push, NVC0_3D(CB_BIND(4)), 1);
PUSH_DATA (push, 0x11);
- BEGIN_NVC0(push, SUBC_3D(0x2608), 1);
+ BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
PUSH_DATA (push, 1);
}
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 4c3bb0f..607e97b 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -12,6 +12,7 @@
/* subchannel assignments, compatible with kepler's fixed layout */
#define SUBC_3D(mthd) 0, (mthd)
#define N...
2017 Mar 13
0
[ANNOUNCE] xf86-video-nouveau 1.0.14
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update nvc0_3d, add gm107_texture for new TIC format
nvc0: make use of the new hwdefs for TEX_CB_INDEX
nvc0: rename BEGIN_IMC0 to IMMED_NVC0
nvc0: refactor TIC uploads to allow different specifics per generation
copy: add maxwell/pascal copy engine classes
recognize and accelerate GM20x
Lyude (2):
Consider CRTCs disabled when DPMS is off
Bump version to 1.0.14
g...
2017 Mar 13
0
[ANNOUNCE] xf86-video-nouveau 1.0.14
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update nvc0_3d, add gm107_texture for new TIC format
nvc0: make use of the new hwdefs for TEX_CB_INDEX
nvc0: rename BEGIN_IMC0 to IMMED_NVC0
nvc0: refactor TIC uploads to allow different specifics per generation
copy: add maxwell/pascal copy engine classes
recognize and accelerate GM20x
Lyude (2):
Consider CRTCs disabled when DPMS is off
Bump version to 1.0.14
g...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
...*(i0))
#define NVC0_3D_CB_BIND__ESIZE 0x00000020
#define NVC0_3D_CB_BIND__LEN 0x00000005
@@ -1778,6 +1888,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_VERT_COLOR_CLAMP_EN 0x00002600
+#define NVE4_3D_UNK2604 0x00002604
+
+#define NVE4_3D_TEX_CB_INDEX 0x00002608
+#define NVE4_3D_TEX_CB_INDEX__MIN 0x00000000
+#define NVE4_3D_TEX_CB_INDEX__MAX 0x00000010
+
+#define NVE4_3D_UNK260C 0x0000260c
+
#define NVC0_3D_IMAGE(i0) (0x00002700 + 0x20*(i0))
#define NVC0_3D_IMAGE__ESIZE 0x00000020
#define NVC0_3D_IMAGE__LEN 0x0...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
...l GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update nvc0_3d, add gm107_texture for new TIC format
nvc0: make use of the new hwdefs for TEX_CB_INDEX
nvc0: rename BEGIN_IMC0 to IMMED_NVC0
nvc0: refactor TIC uploads to allow different specifics per generation
copy: add maxwell/pascal copy engine classes
recognize and accelerate GM20x
src/Makefile.am | 17 +
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwde...