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...eora decoding process, the goal of each function, modules that had already been implemented (to understand how I can integrate) and to get cpu-time consumed for each function. (1 weeks) 2.In this stage, I will choose the module(s) and will study it deeping. (1 weeks) 3.Write these modules in VHDL, tesbenchs and to do the simulation. (6 weeks) 4.Synthesize and test these modules in FPGA, doing the integration and comunication interface with software and hardware modules. (3 weeks) 5.Write the documentations of the hardware implementations, testbenchs and integration. (1 weeks) This times are just a e...