search for: tempregs

2005/7/24, Chris Lattner <sabre at nondot.org>: > Ah, ok. In that case, you want to put all of the registers in one register > file, and not make the constant register allocatable (e.g. see > X86RegisterInfo.td, and note how the register classes include EBP and ESP, > but do not register allocate them (through the definition of > allocation_order_end()). > > -Chris

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

..., I can not find any llvm::MVT::SimpleValueType which can represents a 96-bit register. Thus, my question is: 1) Does current LLVM backend supports this H/W? 2) If yes, how can I write the type of the register class in my .td file? (Which value should I fill in the following 'XXX' ?) def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,...

...bit register. > > > Thus, my question is: > > > 1) Does current LLVM backend supports this H/W? > > 2) If yes, how can I write the type of the register class in my .td   > > file? > > > (Which value should I fill in the following 'XXX' ?) > > def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3,   > > R4, R5, R6, R7, R8, R9, > >                                                    R10, R11, R12,   > > R13, R14, R15, R16, R17, R18, R19, > >                                                    R20, R21, R2...

...ch can > represents a 96-bit register. > > Thus, my question is: > > 1) Does current LLVM backend supports this H/W? > 2) If yes, how can I write the type of the register class in my .td > file? > > (Which value should I fill in the following 'XXX' ?) > def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > R4, R5, R6, R7, R8, R9, > R10, R11, R12, > R13, R14, R15, R16, R17, R18, R19, > R20, R21, R22, > R23, R24,...

Why are you reverting patches for any area that you have no authorization for ? No build was broken. This patch is fine. I am authorized to check in to the Mips area and Daniel is the maintainer for that area. On 06/08/2014 02:13 AM, Alp Toker wrote: > Author: alp > Date: Sun Jun 8 04:13:42 2014 > New Revision: 210424 > > URL:

...gt;> Thus, my question is: >> >>> 1) Does current LLVM backend supports this H/W? >>> 2) If yes, how can I write the type of the register class in my .td >>> file? >> >>> (Which value should I fill in the following 'XXX' ?) >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>> R4, R5, R6, R7, R8, R9, >>> R10, R11, R12, >>> R13, R14, R15, R16, R17, R18, R19, >>> R20,...

...gt;> Thus, my question is: >> >>> 1) Does current LLVM backend supports this H/W? >>> 2) If yes, how can I write the type of the register class in my .td >>> file? >> >>> (Which value should I fill in the following 'XXX' ?) >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>> R4, R5, R6, R7, R8, R9, >>> R10, R11, R12, >>> R13, R14, R15, R16, R17, R18, R19, >>> R20,...

...question is: > > >>> 1) Does current LLVM backend supports this H/W? > >>> 2) If yes, how can I write the type of the register class in my .td > >>> file? > > >>> (Which value should I fill in the following 'XXX' ?) > >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > >>> R4, R5, R6, R7, R8, R9, > >>>                                                    R10, R11, R12, > >>> R13, R14, R15, R16, R17, R18, R19, > >>>                                    ...

...Does current LLVM backend supports this H/W? >>>>> 2) If yes, how can I write the type of the register class in >>>>> my .td >>>>> file? >> >>>>> (Which value should I fill in the following 'XXX' ?) >>>>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>>>> R4, R5, R6, R7, R8, R9, >>>>> R10, R11, R12, >>>>> R13, R14, R15, R16, R17, R18, R19, >>>>>...

...question is: > > >>> 1) Does current LLVM backend supports this H/W? > >>> 2) If yes, how can I write the type of the register class in my .td > >>> file? > > >>> (Which value should I fill in the following 'XXX' ?) > >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > >>> R4, R5, R6, R7, R8, R9, > >>>                                                    R10, R11, R12, > >>> R13, R14, R15, R16, R17, R18, R19, > >>>                                    ...

...Does current LLVM backend supports this H/W? >>>>> 2) If yes, how can I write the type of the register class in >>>>> my .td >>>>> file? >> >>>>> (Which value should I fill in the following 'XXX' ?) >>>>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>>>> R4, R5, R6, R7, R8, R9, >>>>> R10, R11, R12, >>>>> R13, R14, R15, R16, R17, R18, R19, >>>>>...

..._add_dst_param and make it shader_arb_get_dst_param. wined3d: Simplify shader_hw_map2gl. wined3d: Tidy up shader_hw_rsq_rcp. wined3d: Standardize pshader_hw_texkill. wined3d: Tidy up pshader_hw_tex. wined3d: Fix 1.4 pshader projection in ARB. wined3d: Separate Tx tempregs from Tx varyings in ARB. wined3d: Tidy up pshader_hw_cnd. wined3d: Tidy up pshader_hw_cmp. wined3d: Tidy up pshader_hw_dp2add. wined3d: Tidy up pshader_hw_texreg2rgb and friends. wined3d: Fix a few more hardcoded pixel shader registers. wined3d: Fix remaining inc...