search for: tegra186

...bit ttm gpio_keys > drm_kms_helper drm drm_panel_orientation_quirks(P) syscopy > area sysfillrect sysimgblt fb_sys_fops pps_core host1x > [ 12.050665] CPU: 0 PID: 261 Comm: systemd-udevd Tainted: P S > 4.15.0-rc3-next-20171214-ARCH-AEDEN+ #3 > [ 12.050666] Hardware name: NVIDIA Tegra186 P2771-0000 Development Board > (DT) > [ 12.050668] pstate: 80000005 (Nzcv daif -PAN -UAO) > [ 12.050675] pc : mutex_lock+0x28/0x58 > [ 12.050676] lr : mutex_lock+0x1c/0x58 > [ 12.050677] sp : ffff00000a33b970 > [ 12.050679] x29: ffff00000a33b970 x28: ffff000009527a20 &gt...

...drm drm_panel_orientation_quirks(P) host1x > dwmac_dwc_qos_eth stmmac_platform stmmac ptp pps_core > syscopyarea sysfillrect sysimgblt fb_sys_fops > [ 16.894001] CPU: 3 PID: 381 Comm: Xorg Tainted: P S > 4.15.0-rc3-next-20171214-ARCH-AEDEN+ #3 > [ 16.903546] Hardware name: NVIDIA Tegra186 P2771-0000 Development Board (DT) > [ 16.910578] pstate: 60000005 (nZCv daif -PAN -UAO) > [ 16.915527] pc : nouveau_bo_new+0x450/0x4d0 [nouveau] > [ 16.920729] lr : nouveau_bo_new+0x78/0x4d0 [nouveau] > [ 16.925678] sp : ffff00000a34bb40 > [ 16.928980] x29: ffff00000a34bb60...

On Thu, Dec 21, 2017 at 12:32:39PM -0500, Anthony Eden wrote: > Hi Thierry, > > Thanks for the patch. I applied on top of linux-next-2017-12-14. > Different output this time. > > [ 11.862495] WARNING: CPU: 1 PID: 254 at > drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c:391 This looks like something that could potentially be fixed by this:

...gpio_keys drm_kms_helper drm drm_panel_orientation_quirks(P) host1x dwmac_dwc_qos_eth stmmac_platform stmmac ptp pps_core syscopyarea sysfillrect sysimgblt fb_sys_fops [ 16.894001] CPU: 3 PID: 381 Comm: Xorg Tainted: P S 4.15.0-rc3-next-20171214-ARCH-AEDEN+ #3 [ 16.903546] Hardware name: NVIDIA Tegra186 P2771-0000 Development Board (DT) [ 16.910578] pstate: 60000005 (nZCv daif -PAN -UAO) [ 16.915527] pc : nouveau_bo_new+0x450/0x4d0 [nouveau] [ 16.920729] lr : nouveau_bo_new+0x78/0x4d0 [nouveau] [ 16.925678] sp : ffff00000a34bb40 [ 16.928980] x29: ffff00000a34bb60 x28: ffff8001f67f0598 [...

On Tegra186, powergating is handled by the BPMP power domain provider and the "legacy" powergating API is not available. Therefore skip these calls if we are attached to a power domain. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/te...

...oblem you have encountered. > > I don't think I have. Recent chips have similar capabilities, but they > don't have the restriction to a context bank, as far as I understand. > Adding Mikko who's had more exposure to this. IIRC the only way I've gotten Host1x to work on Tegra186 with IOMMU enabled is doing the equivalent of this patch (or actually using the DMA API, which may be possible but has some potential issues). As you said, we don't have a limitation regarding the context bank or similar - Host1x handles context switching by changing the sent stream ID on...

...veau(+) ptp tegra_drm i2c_algo_bit ttm drm_kms_helper drm drm_panel_orientation_quirks(P) syscopyarea sysfillrect sysimgblt fb_sys_fops host1x pps_core [ 11.916358] CPU: 1 PID: 254 Comm: systemd-udevd Tainted: P S 4.15.0-rc3-next-20171214-ARCH-AEDEN+ #3 [ 11.926685] Hardware name: NVIDIA Tegra186 P2771-0000 Development Board (DT) [ 11.933722] pstate: 80000005 (Nzcv daif -PAN -UAO) [ 11.939021] pc : gf100_vmm_new_+0x60/0x128 [nouveau] [ 11.944234] lr : gf100_vmm_new+0x70/0x98 [nouveau] [ 11.949015] sp : ffff00000a2234a0 [ 11.952321] x29: ffff00000a2234b0 x28: ffff0000091cf000 [ 1...

On Wed, Apr 25, 2018 at 12:10:47PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding at nvidia.com> > > Depending on the kernel configuration, early ARM architecture setup code > may have attached the GPU to a DMA/IOMMU mapping that transparently uses > the IOMMU to back the DMA API. Tegra requires special handling for IOMMU > backed buffers (a special bit in

...th and at least there is somebody else > out there in the cold dark world that understands my pain. :) This doesn't actually fix anything on 64-bit ARM, and oddly enough I haven't run into this issue myself on 64-bit ARM either. I think the reason is that I haven't tested Nouveau on Tegra186 yet, which is the first SoC which has an ARM SMMU. On prior 64-bit ARM chips we've used the custom Tegra SMMU and that driver simply forbids creating any DMA domains, so it will allow only explicit usage of the IOMMU API. There is code in the generic DMA/IOMMU integration layer to not use the D...

...However, I did find out that checking out the drm/nouveau directory at commit "drm/nouveau/kms/nv50: use the correct state for base channel notifier setup" makes things work again. I'll continue to take look, though bisecting is a bit harder than usual due to some other issues in Tegra186 recently, so any pointers in the right direction would be useful :) Thanks, Mikko

...ra because from the GPU's point of view all memory is now contiguous. However, these patches only make sure that buffers are mapped properly and don't try to enable big pages. Also note that mapping through the IOMMU comes at a slight cost, so this may not always be desirable. However, with Tegra186 and later it's currently not possible (from a DMA API point of view) to map only a subset of buffers through the IOMMU, so any such optimization is deferred. Furthermore, the ARM SMMU driver currently enforces the use of the SMMU by default, so there not much of a choice at the moment. Finally...

...+) tegra_drm(+) i2c_algo_bit ttm gpio_keys drm_kms_helper drm drm_panel_orientation_quirks(P) syscopy area sysfillrect sysimgblt fb_sys_fops pps_core host1x [ 12.050665] CPU: 0 PID: 261 Comm: systemd-udevd Tainted: P S 4.15.0-rc3-next-20171214-ARCH-AEDEN+ #3 [ 12.050666] Hardware name: NVIDIA Tegra186 P2771-0000 Development Board (DT) [ 12.050668] pstate: 80000005 (Nzcv daif -PAN -UAO) [ 12.050675] pc : mutex_lock+0x28/0x58 [ 12.050676] lr : mutex_lock+0x1c/0x58 [ 12.050677] sp : ffff00000a33b970 [ 12.050679] x29: ffff00000a33b970 x28: ffff000009527a20 [ 12.050682] x27: ffff8001c5089...

...he drm/nouveau directory at commit >> "drm/nouveau/kms/nv50: use the correct state for base channel notifier >> setup" makes things work again. >> >> I'll continue to take look, though bisecting is a bit harder than >> usual due to some other issues in Tegra186 recently, so any pointers >> in the right direction would be useful :) >> >> Thanks, >> Mikko >> _______________________________________________ >> Nouveau mailing list >> Nouveau at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/list...

On Tegra186 systems with certain firmware revisions, leaving the GPU in reset can cause a hang. To prevent this, don't leave the GPU in reset. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 3 --- 1 file changed, 3 deletions(-) di...

On 06/09/2017 10:25 PM, Mikko Perttunen wrote: > On Tegra186, powergating is handled by the BPMP power domain provider > and the "legacy" powergating API is not available. Therefore skip > these calls if we are attached to a power domain. Thanks Mikko, Taken all 3 patches into my tree. Ben. > > Signed-off-by: Mikko Perttunen <mpe...

...> checking out the drm/nouveau directory at commit "drm/nouveau/kms/nv50: > use the correct state for base channel notifier setup" makes things work > again. > > I'll continue to take look, though bisecting is a bit harder than usual > due to some other issues in Tegra186 recently, so any pointers in the > right direction would be useful :) > > Thanks, > Mikko > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the