Displaying 6 results from an estimated 6 matches for "tdst".
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2008 Sep 23
3
[LLVMdev] A question about instruction operands.
I have a question:
In the pattern below from X86
def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
"inc{b}\tdst",
[(set GR8:$dst, (add GR8:$src, 1))]>;
Since we are emitting only "inc $dst",
What makes sure that the $src and $dst are same register?
- Sanjiv
2008 Sep 23
0
[LLVMdev] A question about instruction operands.
sanjiv gupta wrote:
> I have a question:
> In the pattern below from X86
>
> def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
> "inc{b}\tdst",
> [(set GR8:$dst, (add GR8:$src, 1))]>;
>
> Since we are emitting only "inc $dst",
> What makes sure that the $src and $dst are same register?
>
> - Sanjiv
It's enclosed inside :
let isTwoAddress = 1 in {
...
}
(you'll need to scroll up a fair amo...
2008 Sep 23
2
[LLVMdev] A question about instruction operands.
On Tue, 2008-09-23 at 13:33 +0100, Richard Osborne wrote:
> sanjiv gupta wrote:
> > I have a question:
> > In the pattern below from X86
> >
> > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
> > "inc{b}\tdst",
> > [(set GR8:$dst, (add GR8:$src, 1))]>;
> >
> > Since we are emitting only "inc $dst",
> > What makes sure that the $src and $dst are same register?
> >
> > - Sanjiv
> It's enclosed inside :
>
> let isTwoAddress = 1 in {
&g...
2008 Sep 22
2
[LLVMdev] A question.
I found that LLVM were using Binutils to assemble the Assembly Code to the Machine Code, so I have a question, why LLVM don't direct generate the machine code?
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2008 Sep 22
0
[LLVMdev] A question.
On Sep 22, 2008, at 13:36, 罗勇刚 wrote:
> I found that LLVM were using Binutils to assemble the Assembly Code
> to the Machine Code, so I have a question, why LLVM don't direct
> generate the machine code?
There was a protracted and rather uninteresting discussion of this
matter on this list some months ago. I'll summarize the outcome of
that thread briefly:
LLVM does
2008 Sep 23
0
[LLVMdev] A question about instruction operands.
...e, 2008-09-23 at 13:33 +0100, Richard Osborne wrote:
>
>> sanjiv gupta wrote:
>>
>>> I have a question:
>>> In the pattern below from X86
>>>
>>> def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
>>> "inc{b}\tdst",
>>> [(set GR8:$dst, (add GR8:$src, 1))]>;
>>>
>>> Since we are emitting only "inc $dst",
>>> What makes sure that the $src and $dst are same register?
>>>
>>> - Sanjiv
>>>
>> It's enclosed inside...