Displaying 5 results from an estimated 5 matches for "tcwl".
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tcl
2013 Jul 18
1
[PATCH 02/11] drm/nv50/pm: Fix last timing register in NVA3+, fix typo in NV50
...t drm_device *dev, u32 freq,
break;
}
+ tUnk_3_2 = (boot->reg[3] & 0x00ff0000) >> 16;
+ if(tUnk_3_2 == 0) {
+ tUnk_3_2 = 0x16;
+ }
+
t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
@@ -102,7 +108,9 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
e->tRCDWR << 8 |
e->tRCDRD);
- t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
+ t->reg[3] = (tUnk_3_2 << 16) | (e->tCL - 1);
+
+ t->reg[4] = (unk20 &l...
2013 Jul 18
0
[PATCH 02/11] drm/nv50/pm: Fix last timing register in NVA3+, fix typo in NV50
...> + tUnk_3_2 = (boot->reg[3] & 0x00ff0000) >> 16;
> + if(tUnk_3_2 == 0) {
> + tUnk_3_2 = 0x16;
> + }
> +
> t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
>
> t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
> @@ -102,7 +108,9 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
> e->tRCDWR << 8 |
> e->tRCDRD);
>
> - t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
> + t->reg[3] = (tUnk_3_2 << 16) | (e->tCL -...
2012 Jun 25
1
[PATCH 1/2] drm/nouveau/pm: Prepare for more GDDR5 MR values
...rs/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index b8fa77d..fe242a3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -352,7 +352,7 @@ struct nouveau_pm_memtiming {
int id;
u32 reg[9];
- u32 mr[4];
+ u32 mr[9];
u8 tCWL;
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 1e1483e..1d290ab 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -626,6 +626,7 @@ nouveau_mem_gddr5_mr(struct nouveau_device *ndev, u32 freq,...
2014 Aug 25
0
[PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.
...94" name="MEM_TIMINGS_1" variants="NVC0-">
> + <bitfield high="3" low="0" name="tCL">
> + <doc> Row Cycle time. </doc>
> + </bitfield>
> + <bitfield high="13" low="7" name="tCWL">
> + <doc> CAS# Write Latency. </doc>
> + </bitfield>
> </reg32>
>
> <reg32 offset="0x298" name="MEM_TIMINGS_2" variants="NVC0-">
> + <bitfield high="15" low="8" name="tWT...
2014 Aug 25
12
[PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.
...g32 offset="0x294" name="MEM_TIMINGS_1" variants="NVC0-">
+ <bitfield high="3" low="0" name="tCL">
+ <doc> Row Cycle time. </doc>
+ </bitfield>
+ <bitfield high="13" low="7" name="tCWL">
+ <doc> CAS# Write Latency. </doc>
+ </bitfield>
</reg32>
<reg32 offset="0x298" name="MEM_TIMINGS_2" variants="NVC0-">
+ <bitfield high="15" low="8" name="tWTR">
+ <doc> Write...