search for: tcreturnri

...> In this case, the problem is that CTR and CTR8 are allocatable > because CTRRC and CTRRC8 are allocatable. You can set 'isAllocatable > = 0' in those register classes. Thanks for explaining! [We should add this to the docs somewhere]. > > Unfortunately, that breaks your TCRETURNri instructions. Sorry! I'm guessing that I can rewrite TCRETURN to reference CTR/CTR8 directly. I'll have to try that. > > Singleton register classes are dangerous because it is so easy to > extend the live range of virtual registers without checking for > interference. If you...

...ich by their nature can't >> be in SSA form. Lang and I have been trying to come up with some >> rules, but we haven't found the right set yet. > [We should add this to the docs somewhere]. http://llvm.org/bugs/show_bug.cgi?id=13058 >> Unfortunately, that breaks your TCRETURNri instructions. Sorry! > > I'm guessing that I can rewrite TCRETURN to reference CTR/CTR8 > directly. I'll have to try that. That should be possible, yes. /jakob

...optimizations like dead code elimination. (You don't want to DCE a stack pointer update). In this case, the problem is that CTR and CTR8 are allocatable because CTRRC and CTRRC8 are allocatable. You can set 'isAllocatable = 0' in those register classes. Unfortunately, that breaks your TCRETURNri instructions. Sorry! Singleton register classes are dangerous because it is so easy to extend the live range of virtual registers without checking for interference. If you accidentally cross two live ranges, you get horrible spilling as you've seen. We try to use explicit unallocatable physreg...

On Thu, 7 Jun 2012 22:14:00 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > > > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > > Predecessors according to CFG: BB#0 BB#1 > > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, > >

...BB.getLastNonDebugInstr(); assert((MBBI->getOpcode() == ARM::tBX_RET || - MBBI->getOpcode() == ARM::tPOP_RET) && - "Can only insert epilog into returning blocks"); + MBBI->getOpcode() == ARM::tPOP_RET || + MBBI->getOpcode() == ARM::TCRETURNri) + && "Can only insert epilog into returning blocks " + "and tail calls with address in regs."); + + bool IsTailCallReturn = false; + if (MBBI->getOpcode() == ARM::TCRETURNri) + IsTailCallReturn = true; + DebugLoc dl = MBBI->getDebugLoc(...

...9;t be in SSA form. Lang and I have been trying to come up with > >> some rules, but we haven't found the right set yet. > > > [We should add this to the docs somewhere]. > > http://llvm.org/bugs/show_bug.cgi?id=13058 > > >> Unfortunately, that breaks your TCRETURNri instructions. Sorry! > > > > I'm guessing that I can rewrite TCRETURN to reference CTR/CTR8 > > directly. I'll have to try that. > > That should be possible, yes. As it turns out, I don't need to (the patterns in question are never actually used in the current...

...[]>; + Why are these needed? They don't look any different from normal add and subtraction instructions. Why not just use ADJCALLSTACKDOWN and ADJCALLSTACKUP? 6. + } else if (RetOpcode == X86::TCRETURNdi) { + // a tailcall adjust the stack ... + } else if (RetOpcode == X86::TCRETURNri) { + MBBI = prior(MBB.end()); Seems like there are quite a bit of duplicate code between the 2 cases. Please refactor. 7. X86TargetLowering::X86TargetLowering(TargetMachine &TM) : TargetLowering(TM) { + IsLastCallTailCall = false; This is probably not a good idea. You are assuming...

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

...d? They don't look any different from normal add > and subtraction instructions. Why not just use ADJCALLSTACKDOWN and > ADJCALLSTACKUP? > > 6. > + } else if (RetOpcode == X86::TCRETURNdi) { > + // a tailcall adjust the stack > ... > + } else if (RetOpcode == X86::TCRETURNri) { > + MBBI = prior(MBB.end()); > > Seems like there are quite a bit of duplicate code between the 2 > cases. Please refactor. Okay dokey > 7. > X86TargetLowering::X86TargetLowering(TargetMachine &TM) > : TargetLowering(TM) { > + IsLastCallTailCall = false; >...