search for: tarnsit

...; > say [%s0,%s1,%GR0,%GR1]? > > Depending on how you defined the aliases, they aren't necessarily > transitive. I'd like at the <yourtarget>GenRegisterInfo.inc file, > and see > what it lists as the aliases for each reg. Done. And I looked into the tblgen code. Tarnsitivity is not ensured by tblgen in any form, since it does not compute it. What it ensures is the commutativity of aliases, i.e. if A aliases B, then B aliases A. I think it would make sense if tblgen would compute a transitive closure automatically for alias sets, because I can hardly imagine non-tr...

...ibute syntax. >> Depending on how you defined the aliases, they aren't necessarily >> transitive. I'd like at the <yourtarget>GenRegisterInfo.inc file, >> and see >> what it lists as the aliases for each reg. > > Done. And I looked into the tblgen code. Tarnsitivity is not ensured by > tblgen in any form, since it does not compute it. What it ensures is > the commutativity of aliases, i.e. if A aliases B, then B aliases A. I > think it would make sense if tblgen would compute a transitive closure > automatically for alias sets, because I can h...

On Tue, 10 Oct 2006, Roman Levenstein wrote: >>> such a call instruction? >> >> Why not just make the asm string be "call __fsub64"? > > Well, of course it would be the best solution. But the interesting part > is that I need to generate the machine code directly because for > different reasons use of a system assembler is not an option. As a ok. >

Hi, >> My target supports only f64 at the moment. >> Question: How can I tell LLVM that float is the same as double on my >> target? May be by assigning the same register class to both MVT::f32 ?> and MVT::f64? >Just don't assign a register class for the f32 type. This is what the >X86 backend does when it is in "floating point stack mode". This will