Displaying 2 results from an estimated 2 matches for "targetscheme".
2011 Apr 14
0
[LLVMdev] Fwd: LLVM Scheduler and Itinieraries: Negative latency?
...nything
higher than one, the scheduler think that the instruction occupy the
functional unit for that many cycles but in my case this is not true,
the "pipe" is pipelined. Structural hazards cannot occur in the
pipeline, but data hazards can. I looked at the example in
include/llvm/Target/TargetScheme.td, in that example a value of 1 for
machine cycles and higher values for when the result is ready (3) and
when the operands are referenced (2) are showed. Do you have any hints
on what I am doing wrong, since the example seem to show that this
"negative latency" should work?
kind regar...
2011 Apr 14
3
[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
Hello,
While trying to create back end in LLVM I have stumbled upon a problem
I have trouble to get past, hopefully someone can give me hints on
what I am doing wrong. The problem is that the assertion in the file
ScheduleDAGList.cpp row 187 is triggered: "Negative latency". How does
this happen?
As background:
My target has one issue unit, therefore my Schedule.td file only