Displaying 2 results from an estimated 2 matches for "targetpat".
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2014 Aug 05
2
[LLVMdev] Concerning not relevant argument count in TableGen Patterns.
...s1:$rs),
(ins Regs2:$rt),
!strconcat(instr_asm, "\t$rt, $rs"),
[], NoItinerary> {
let imm16 = 0;
}*
where *Regs1* and *Regs2* are corresponding *RegisterClasses*.
Then I need to define the instruction:
*def MOVInstr : Mymov<0x2, "mov">;*
*def : TargetPat<(int_myintrinsicname), (MOVInstr)>;* /// error: In
anonymous.4: Instruction 'MOVInstr' expects more operands than were
provided./
int the corresponding /inclue/llvm/IR/IntrinsicsTarget.td/ file:
*def int_myintrinsicname : Intrinsic< [llvm_i16_ty], [],
[<IntrinsicProperty>...
2014 Jun 10
2
[LLVMdev] Regarding Instruction definition in LLVM backend
...RAND_IMMEDIATE";
}
class SII<bits<6> op, string instr_asm, Operand Imm> :
FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm,
"\t$val"), [], IIAlu> {
let rs = 0;
let rt = 0;
}
def MOV : SII<0x21, "mov", simm16>;
def : TARGETPat<(int_my_builtin_function_name (imm:$val)), (MOV imm:$val)>;
I just found that the base Instruction class has Defs and Uses lists where
it is possible to pass the Registers, but actually I could not use them for
my situation.
I think that I should have Registers in a class "SII", f...