Displaying 20 results from an estimated 123 matches for "targetpassconfig".
2018 Dec 28
2
Advice for Porting SafeStack to New Pass Manager
Hello,
I'm in the process of creating a pass for the new PM for SafeStack
which is only available as a part of the legacy PM. The only thing
bugging me is in regards to the TargetPassConfig analysis. Whereas
most other passes/analyses I have seen separate the logic between the
actual pass and anything it does to the IRUnits it runs over are in 2
separate classes, TargetPassConfig has them both in the same class and
many other analysis inherit from this class as well. I also do not
thi...
2018 Dec 29
0
Advice for Porting SafeStack to New Pass Manager
On 12/28/18 10:09 PM, Leonard Chan via llvm-dev wrote:
> Hello,
>
> I'm in the process of creating a pass for the new PM for SafeStack
> which is only available as a part of the legacy PM. The only thing
> bugging me is in regards to the TargetPassConfig analysis. Whereas
> most other passes/analyses I have seen separate the logic between the
> actual pass and anything it does to the IRUnits it runs over are in 2
> separate classes, TargetPassConfig has them both in the same class and
> many other analysis inherit from this class as wel...
2017 Jan 05
3
LLVMTargetMachine with optimization level passed from clang.
I want the optimization to be turned on at -O1 and above.
In my case, it is a target independent back-end pass. (Eg:
MachinePipeliner)
On 2017-01-04 18:10, Mehdi Amini wrote:
>> On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev
>> <llvm-dev at lists.llvm.org> wrote:
>>
>> I see the BackendUtil.cpp of Clang creates the TargetMachine with
>> the
2017 Jan 06
2
LLVMTargetMachine with optimization level passed from clang.
...ple.com [mailto:jpaquette at apple.com]
Sent: Thursday, January 5, 2017 12:24 PM
To: sgundapa at codeaurora.org
Cc: LLVM Developers <llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] LLVMTargetMachine with optimization level passed from clang.
Most of the stuff you’re looking for lives in TargetPassConfig.cpp. There are a few examples of how you might do it that live in there too.
What it comes down to is finding the place you want your pass to live and sticking in some logic like this in there:
if (getOptLevel() != CodeGenOpt::None)
addPass(&MyPassID);
A lot of passes are added in just T...
2020 Aug 11
2
opt - replicating multiple passes from -O3 -debug-pass=Executions
...seems there are two passes being run. When I run the flags indicated for
the two passes specified in the 'Pass Arguments:' as two sequential opt
processes or a single opt process with the concatenated flags I get a
different binary result compared to the O3 run. (Note I had to remove the
-targetpassconfig flag and add -spec-exec-only-if-divergent-target to the
second pass to get my run to match O3's second pass.)
Comparing the -debug-pass=Executions from my runs with the O3 run, it seems
the first pass in my run has additional 'TargetLibrary Information',
'Target Pass Configuration&...
2020 Sep 07
2
New PM for target-specific pre-isel IR passes
Hi,
Is there a mechanism in place to use the new pass manager with target-specific passes added (at the moment) via addIRPasses in TargetPassConfig?
I did see any code related to that, did I miss something? Is it in plan?
--
Krzysztof Parzyszek kparzysz at quicinc.com AI tools development
2017 Jan 06
3
LLVMTargetMachine with optimization level passed from clang.
...pple.com]
> Sent: Thursday, January 5, 2017 12:24 PM
> To: sgundapa at codeaurora.org
> Cc: LLVM Developers <llvm-dev at lists.llvm.org>
> Subject: Re: [llvm-dev] LLVMTargetMachine with optimization level passed from clang.
>
> Most of the stuff you’re looking for lives in TargetPassConfig.cpp. There are a few examples of how you might do it that live in there too.
>
> What it comes down to is finding the place you want your pass to live and sticking in some logic like this in there:
>
> if (getOptLevel() != CodeGenOpt::None)
> addPass(&MyPassID);
>
> A...
2012 Nov 01
2
[LLVMdev] Tail Duplication Questions
Eli Friedman <eli.friedman at gmail.com> writes:
>> Ah. So is the MachineFunction version expected to work correctly?
>
> It's part of the default set of CodeGen passes.
It is? Was that true in 3.1? I can't see where it is initialized in
llc. I probably missed something important. :)
Thanks!
-David
2012 Nov 01
0
[LLVMdev] Tail Duplication Questions
http://llvm.org/viewvc/llvm-project/llvm/tags/RELEASE_31/final/lib/CodeGen/Passes.cpp?revision=156747&view=markup
void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication.
if (addPass(EarlyTailDuplicateID) != &NoPassID)
printAndVerify("After Pre-RegAlloc TailDuplicate");
/// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOp...
2013 Feb 17
1
[LLVMdev] Overhauling the command-line processing/codegen options code
...rtual method to all passes that allows clients to pass arbitrary options, like a "virtual void setOption(StringRef Option, StringRef Value) {}". Though this use-case seems very rare…
It is generally convenient to decouple pass configuration from construction. CodeGen does this using the TargetPassConfig analysis. It allows pass instantiation to be configured using only Pass IDs.
Right now it's only used for subtarget options. But it would be nice to unify all codegen options for transparency and discoverability. e.g. I need to know why clang/opt/llc is not generating the same code for some t...
2012 Dec 07
0
[LLVMdev] Interprocedural Register Allocation
...4!
0 llc 0x0000000001453dfe
1 llc 0x00000000014542fa
2 libpthread.so.0 0x00007f020b750cb0
3 libc.so.6 0x00007f020a99f425 gsignal + 53
4 libc.so.6 0x00007f020a9a2b8b abort + 379
5 llc 0x000000000143b1a6
6 llc 0x0000000000f3cb02 llvm::TargetPassConfig::addPass(void
const*) + 146
7 llc 0x0000000000f3ddef
llvm::TargetPassConfig::addCGRegAlloc(llvm::CallGraphSCCPass*) + 47
8 llc 0x0000000000f3d7df
llvm::TargetPassConfig::addMachinePasses() + 719
9 llc 0x0000000000e5a3af
10 llc 0x0000000000e5994c
ll...
2012 Nov 02
2
[LLVMdev] Interprocedural Register Allocation
On Oct 31, 2012, at 1:41 PM, Madhusudan C.S <madhusudancs at gmail.com> wrote:
> I have spent last 4 weeks trying to figure out how to implement
> Interprocedural Register Allocation. I must admit that I was really
> overwhelmed with LLVM's codebase while trying to figure this out :)
> There is so much to know! I think I have reached a point where I
> have some sort of
2012 Jun 28
2
[LLVMdev] Why some registered passes are not available through opt?
Dear LLVM,
I'm trying to understand why opt tool does not know some of the
registered passes, for example, -targetpassconfig, -gc-lowering,
-unreachableblockelim, -unreachableblockelim, -stack-protector,
-machinemoduleinfo. This prevents me from using bugpoint to reduce the
crash in backend. As I understand, they should be registered and
available through the command line in the same way as all other
passes, shouldn'...
2013 Jan 07
4
[LLVMdev] instruction scheduling issue
On 1/7/2013 2:15 PM, Xu Liu wrote:
>
> This would be ideal. How can I do the instrumentation pass after the
> instruction scheduling?
You could derive your own class from TargetPassConfig, and add the
annotation pass in YourDerivedTargetPassConfig::addPreEmitPass. This
will add your annotation pass very late, just before the final code is
emitted. If you're using the X86 target, then the class and the
function is already there:
lib/Target/X86/X86TargetMachine.cpp:
bool X...
2012 Jun 29
2
[LLVMdev] Why some registered passes are not available through opt?
...alysis/transformation and codegen passes? I would
like to modify bugpoint to work on this end.
Thanks,
- D.
2012/6/29 Duncan Sands <baldrick at free.fr>:
> Hi Dima,
>
>> I'm trying to understand why opt tool does not know some of the
>> registered passes, for example, -targetpassconfig, -gc-lowering,
>> -unreachableblockelim, -unreachableblockelim, -stack-protector,
>> -machinemoduleinfo. This prevents me from using bugpoint to reduce the
>> crash in backend. As I understand, they should be registered and
>> available through the command line in the same w...
2015 Dec 04
2
link error for analysis pass
Hi Mehdi,
I meant when I build the LLVM and it will give the following errors:
make[2]: Entering directory `/home/alex/new/llvm-obj/tools/llc'
llvm[2]: Linking Debug+Asserts executable llc
/home/alex/new/llvm-obj/Debug+Asserts/lib/libLLVMCodeGen.a(Passes.o): In
function `llvm::TargetPassConfig::addIRPasses()':
/home/alex/new/llvm-3.1.src/lib/CodeGen/Passes.cpp:295: undefined reference
to `llvm::createMyAliasAnalysisPass()'
collect2: ld returned 1 exit status
make[2]: *** [/home/alex/new/llvm-obj/Debug+Asserts/bin/llc] Error 1
make[2]: Leaving directory `/home/alex/new/llvm-obj/to...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
I overrode getInstrLatency and did some printing to see what is available
there. It looks like the registers are still virtual at that point when
getInstrLatency is called - is that correct? (we needed to make some
decisions based on actual registers that have been assigned since some
registers are reserved as address space pointers and we could vary the
latency based on which address space
2012 Jun 29
0
[LLVMdev] Why some registered passes are not available through opt?
Hi Dima,
> I'm trying to understand why opt tool does not know some of the
> registered passes, for example, -targetpassconfig, -gc-lowering,
> -unreachableblockelim, -unreachableblockelim, -stack-protector,
> -machinemoduleinfo. This prevents me from using bugpoint to reduce the
> crash in backend. As I understand, they should be registered and
> available through the command line in the same way as all other...
2012 Jun 29
0
[LLVMdev] Why some registered passes are not available through opt?
...would
> like to modify bugpoint to work on this end.
>
> Thanks,
> - D.
>
> 2012/6/29 Duncan Sands <baldrick at free.fr>:
>> Hi Dima,
>>
>>> I'm trying to understand why opt tool does not know some of the
>>> registered passes, for example, -targetpassconfig, -gc-lowering,
>>> -unreachableblockelim, -unreachableblockelim, -stack-protector,
>>> -machinemoduleinfo. This prevents me from using bugpoint to reduce the
>>> crash in backend. As I understand, they should be registered and
>>> available through the command li...
2013 Oct 05
0
[LLVMdev] How to supply a non-default constructor to RegisterPass ?
...ion.
- If you have a pass that can be configured in different modes, get the mode from the current context within the pass. Maybe a Function attribute can be used, or ask TargetMachine/TargetOptions within backend passes.
- Get what you need from an existing ImmutablePass, like TargetTransformInfo, TargetPassConfig, or create your own Immutable pass.
-Andy