search for: targetopcode

Hello, Could someone please explain the semantics of TargetOpcode::KILL? Specifically, in this example, which register is killed? Would it be legal for operands 0 and 1 to refer to different registers? 128B %R3<def> = KILL %R3, %R3_1<imp-use>, %R3_23<imp-use> (In my out-of-tree target, %R3 is a <4xi32> register, %R3_1 is an i32 su...

...tely following fmuladd. RegReductionPQBase::getNodePriority() (in CodeGen/SelectionDAG/ScheduleDAGRRList.cpp) normally returns the SethiUllmanNumber for a node, but there's a few special cases. ISD::TokenFactor and ISD::CopyToReg return a 0, to push them closer to their uses, and similarly for TargetOpcode::EXTRACT_SUBREG, TargetOpcode::SUBREG_TO_REG, and TargetOpcode::INSERT_SUBREG. There is also a special case for instructions that are the end of a computational chain, or at the beginning, based on if the instruction has 0 predecessors or 0 successors. Our fence instruction has 2 (constant) predec...

Hi *, to decide in which namespace tablegen should place the instruction-enum, tablegen iterates over CodeGenTarget instructions until it finds an Instruction with a namespace other than "TargetInstInfo".. but this is wrong, as internal Instructions now use "TargetOpcode" as Namespace.. As Instructions are a map, it is only by chance which is the first instruction it finds - either a user-defined, everything okay - or an internal, which results code like namespace llvm { namespace TargetOpcode { enum { PHI = 0, ... which of course cant compile... Att...

...>getOperand(DstIdx).getSubReg(); TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); ++NumReMats; } else { - BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), - regA).addReg(regB); + unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); + if (regASubIdx) { + BuildMI(*mbbi, mi, mi->getDebugLoc(), + TII->get(TargetOpcode::COPY)). + addReg(regA, Re...

...39;t seem to be a good way to create such a fake use in LLVM (please enlighten us if you know of one), so we are proposing to introduce a new intrinsic (e.g. llvm.fake_use), which would take a single value argument, representing a use of that value. The intrinsic would be lowered to a new invariant TargetOpcode (e.g. FAKE_USE), which serves the same purpose at the MI level. Code emission would simply ignore the new opcode. Frontends could use the intrinsic to extend liveranges of variables as desired. As a first use case, clang would accept a new option (e.g. -fkeep-this-ptr) which would cause a fake use...

...sure we don't emit the same livein copies twice, in case this > + //function is called more than once. > + } else if (def_empty(LiveIns[i].second)) { > // Emit a copy. > BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), > TII.get(TargetOpcode::COPY), LiveIns[i].second) > -- > 1.7.6.4 > > Reposting this as a diff that can be applied via patch -P0 for SVN users. -Tom

...code, TARGET_VAL(ISD::Constant), /* 20*/ OPC_CheckPredicate, 0, // Predicate_Imm_17_31_i16 /* 22*/ OPC_CheckType, MVT::i16, /* 24*/ OPC_MoveParent, /* 25*/ OPC_CheckType, MVT::i32, /* 27*/ OPC_MoveParent, /* 28*/ OPC_CheckType, MVT::i40, /* 30*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0, MVT::i40, 0/*#Ops*/, // Results = #2 /* 36*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0, MVT::i32, 0/*#Ops*/, // Results = #3 /* 42*/ OPC_EmitInteger, MVT::i32, OurTarget::hi16, // Results = #4 /* 45*/ OPC_EmitNode1, TAR...

...g InitializeNativeTargetAsmParser() in my code. Now I have a failure in resolving external libraries, so looking into that (recompiled with --enable-ffi but I now get an error LLVMgold.so not found). Then I hda to disable the following code in lib/Target/X86/X86CodeEmitter.cpp: > case TargetOpcode::INLINEASM: > // We allow inline assembler nodes with empty bodies - they can > // implicitly define registers, which is ok for JIT. > //if (MI.getOperand(0).getSymbolName()[0]) > // report_fatal_error("in X86CodeEmitter.cpp JIT does not support inl...

...e > > this > > > + //function is called more than once. > > > + } else if (def_empty(LiveIns[i].second)) { > > > // Emit a copy. > > > BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), > > > TII.get(TargetOpcode::COPY), LiveIns[i].second) > > > -- > > > 1.7.6.4 > > > > > > > > > > Reposting this as a diff that can be applied via patch -P0 for SVN > > users. > > > > -Tom > > > > > > __________________________________________...

...getAsmParser() in my code. Now I have a failure in resolving external libraries, so looking into that (recompiled with --enable-ffi but I now get an error LLVMgold.so not found). >> >> Then I hda to disable the following code in lib/Target/X86/X86CodeEmitter.cpp: >>> case TargetOpcode::INLINEASM: >>> // We allow inline assembler nodes with empty bodies - they can >>> // implicitly define registers, which is ok for JIT. >>> //if (MI.getOperand(0).getSymbolName()[0]) >>> // report_fatal_error("in X86CodeEmit...

...lass that is likely too small to be reasonable (i.e., below MinRCSize). Cheers, -Quentin > == DstRC) { > MRI->setRegClass(VReg, DstRC); > } > else { > BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), > TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); > VReg = NewVReg; > } > } > } > > This does not work. The logic seems sound though, you are checking an RC (DstRC) and the MI's operand's RegClass, get the common sub, which should either be or not be DstRC, right? >...

...at 7:22 PM Craig Topper <craig.topper at gmail.com> wrote: > CopyToReg is not handle by patterns. It should be passed through isel > unchanged. It’s part of a special list of ISD opcodes that don’t change in > SelectioDAGISel::SelectCodeCommon > > It will then be turned into a TargetOpcode::COPY in > InstrEmitter::EmitSpecialNode when the DAG is turned into MachineInstrs. > > On Sat, Nov 4, 2017 at 7:02 PM Robert Baruch via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> So there's a DAG that looks like this in the debug output: >> >>...

...izeNativeTargetAsmParser() in my code. Now I have a failure in resolving external libraries, so looking into that (recompiled with --enable-ffi but I now get an error LLVMgold.so not found). > > Then I hda to disable the following code in lib/Target/X86/X86CodeEmitter.cpp: >> case TargetOpcode::INLINEASM: >> // We allow inline assembler nodes with empty bodies - they can >> // implicitly define registers, which is ok for JIT. >> //if (MI.getOperand(0).getSymbolName()[0]) >> // report_fatal_error("in X86CodeEmitter.cpp JIT does not...

...me livein copies twice, in case > this > > + //function is called more than once. > > + } else if (def_empty(LiveIns[i].second)) { > > // Emit a copy. > > BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), > > TII.get(TargetOpcode::COPY), LiveIns[i].second) > > -- > > 1.7.6.4 > > > > > > Reposting this as a diff that can be applied via patch -P0 for SVN > users. > > -Tom > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.u...

...ke this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); > else > BuildMI(... TargetOpcode::COPY...) > > The condition is trying to reset the reg class if the DstRC reg class is valid for the operand num of the machine instruction. If the NewVReg register class is not valid for that operand of the machine instruction I want to generate a COPY instruction (as it does now all the ti...

...ize). >> >> Cheers, >> -Quentin >> >> >> == DstRC) { >> MRI->setRegClass(VReg, DstRC); >> } >> else { >> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), >> TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); >> VReg = NewVReg; >> } >> } >> } >> >> This does not work. The logic seems sound though, you are checking an RC >> (DstRC) and the MI's operand's RegClass, get the common sub, which should >>...

So there's a DAG that looks like this in the debug output: Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127> In the instruction selection phase, what pattern would that match? I've constructed this so far: (??? REG16:$dst, i16imm:$src) but the problem is, I can't determine what to use as ???. There is an ISD::CopyToReg enum value, but I don't

...thought to look through PPCFastISel.cpp, since there's some code in there that does fast selection with assumptions of the traditional PowerPC FPU. However, that didn't pan out. Now I'm scratching my head, and looking for help on where to try next, as every place I've found "TargetOpcode::COPY" and "PPC::COPY" appear to be covered already, correctly. Thanks, Justin -------------- next part -------------- A non-text attachment was scrubbed... Name: reduced.ll Type: application/octet-stream Size: 535 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/l...

On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote: > ISDOpcodes.h contains what documentation there is on the semantics of each > opcode. And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in MachineInstr form, but you'll see them with -view-sched-dags, and occasionally before). Tim.

On 21 August 2017 at 11:53, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > One thing to be aware of with this is that (IIRC) tablegen uses the pattern to infer things about the pattern. One example I vaguely remember is that an empty pattern would result in the same effect as hasSideEffects=1 and I think there were others. Thanks for the note - excellent point. Looking at