search for: targetop

...e into a register example is sufficient. Thanks, Simon ________________________________________ From: llvm-dev [llvm-dev-bounces at lists.llvm.org] on behalf of Kevin Choi via llvm-dev [llvm-dev at lists.llvm.org] Sent: Friday, March 9, 2018 8:04 PM To: llvm-dev Subject: [llvm-dev] [SelectionDAG] [TargetOp] How to get sub-half of immediate? Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the '...

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant