Displaying 2 results from an estimated 2 matches for "targetmemorysysteminfo".
2018 Nov 01
2
RFC: System (cache, etc.) model for LLVM
...g (SMT), each can only use 4.
PowerPC's dcbt/dcbtst instruction allows explicitly specifying to the
hardware which streams it should establish. Do the buffer counts
include explicitly and automatically established streams? Do
non-stream accesses (e.g. stack access) count towards
> class TargetMemorySystemInfo {
> const TargetCacheLevelInfo &getCacheLevel(unsigned Level) const;
>
> /// getNumLevels - Return the number of cache levels this target has.
> ///
> unsigned getNumLevels() const;
>
> /// Cache level iterators
> ///
> cachelevel_iterator...
2018 Nov 01
3
RFC: System (cache, etc.) model for LLVM
...Blue Gene/Q: What counts as stream is configurable at
runtime via a hardware register. It supports 3 settings:
* Interpret every memory access as start of a stream
* Interpret a stream when there are 2 consecutive cache misses
* Only establish streams via dcbt instructions.
> >> class TargetMemorySystemInfo {
> >> const TargetCacheLevelInfo &getCacheLevel(unsigned Level) const;
> >>
> >> /// getNumLevels - Return the number of cache levels this target has.
> >> ///
> >> unsigned getNumLevels() const;
> >>
> >> /// C...