search for: targetmemoryinfo

Displaying 4 results from an estimated 4 matches for "targetmemoryinfo".

2011 May 03
5
[LLVMdev] Memory Subsystem Representation
...of this work is to provide Passes with useful information such as cache sizes, resource sharing arrangements, etc. so that they may do transformations to improve memory system performance. Here's what I'm thinking this might look like: - Add two new structures to the TargetMachine class: TargetMemoryInfo and TargetExecutionEngineInfo. - TargetMemoryInfo will initially contain cache hierarchy information. It will contain a list of CacheLevelInfo objects, each of which will specify at least the total size of the cache at that level. It may also include other useful bits like associativity,...
2011 May 03
0
[LLVMdev] Memory Subsystem Representation
...Passes with useful information such > as cache sizes, resource sharing arrangements, etc. so that they may do > transformations to improve memory system performance. > > Here's what I'm thinking this might look like: > > - Add two new structures to the TargetMachine class: TargetMemoryInfo >  and TargetExecutionEngineInfo. > > - TargetMemoryInfo will initially contain cache hierarchy information. >  It will contain a list of CacheLevelInfo objects, each of which will >  specify at least the total size of the cache at that level.  It may >  also include other useful...
2011 May 03
0
[LLVMdev] Memory Subsystem Representation
...of this work is to provide Passes with useful information such as cache sizes, resource sharing arrangements, etc. so that they may do transformations to improve memory system performance. Here's what I'm thinking this might look like: - Add two new structures to the TargetMachine class: TargetMemoryInfo and TargetExecutionEngineInfo. - TargetMemoryInfo will initially contain cache hierarchy information. It will contain a list of CacheLevelInfo objects, each of which will specify at least the total size of the cache at that level. It may also include other useful bits like associativity,...
2009 May 03
1
[LLVMdev] L1, L2 Cache line sizes in TargetData?
Hello, Is there any way for a pass to determine the L1 or L2 cacheline size of the target before the IR is lowered to machine instructions? Thanks, -- Nick Johnson